mirror of
https://github.com/RGBCube/serenity
synced 2025-05-31 09:58:11 +00:00
9b4e6f6a23
This allows us to consolidate printing out all the CPU features into one log statement. Also expose them in /proc/cpuinfo
908 lines
21 KiB
C++
908 lines
21 KiB
C++
/*
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* Copyright (c) 2018-2020, Andreas Kling <kling@serenityos.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#pragma once
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#include <AK/Badge.h>
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#include <AK/Noncopyable.h>
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#include <AK/Vector.h>
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#include <Kernel/PhysicalAddress.h>
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#include <Kernel/VirtualAddress.h>
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#define PAGE_SIZE 4096
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#define GENERIC_INTERRUPT_HANDLERS_COUNT 128
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#define PAGE_MASK ((FlatPtr)0xfffff000u)
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namespace Kernel {
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class MemoryManager;
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class PageDirectory;
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class PageTableEntry;
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struct [[gnu::packed]] DescriptorTablePointer
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{
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u16 limit;
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void* address;
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};
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struct [[gnu::packed]] TSS32
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{
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u16 backlink, __blh;
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u32 esp0;
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u16 ss0, __ss0h;
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u32 esp1;
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u16 ss1, __ss1h;
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u32 esp2;
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u16 ss2, __ss2h;
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u32 cr3, eip, eflags;
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u32 eax, ecx, edx, ebx, esp, ebp, esi, edi;
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u16 es, __esh;
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u16 cs, __csh;
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u16 ss, __ssh;
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u16 ds, __dsh;
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u16 fs, __fsh;
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u16 gs, __gsh;
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u16 ldt, __ldth;
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u16 trace, iomapbase;
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};
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union [[gnu::packed]] Descriptor
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{
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struct {
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u16 limit_lo;
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u16 base_lo;
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u8 base_hi;
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u8 type : 4;
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u8 descriptor_type : 1;
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u8 dpl : 2;
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u8 segment_present : 1;
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u8 limit_hi : 4;
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u8 : 1;
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u8 zero : 1;
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u8 operation_size : 1;
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u8 granularity : 1;
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u8 base_hi2;
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};
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struct {
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u32 low;
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u32 high;
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};
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enum Type {
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Invalid = 0,
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AvailableTSS_16bit = 0x1,
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LDT = 0x2,
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BusyTSS_16bit = 0x3,
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CallGate_16bit = 0x4,
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TaskGate = 0x5,
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InterruptGate_16bit = 0x6,
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TrapGate_16bit = 0x7,
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AvailableTSS_32bit = 0x9,
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BusyTSS_32bit = 0xb,
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CallGate_32bit = 0xc,
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InterruptGate_32bit = 0xe,
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TrapGate_32bit = 0xf,
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};
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void* get_base() const
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{
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u32 b = base_lo;
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b |= base_hi << 16;
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b |= base_hi2 << 24;
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return reinterpret_cast<void*>(b);
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}
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void set_base(void* b)
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{
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base_lo = (u32)(b)&0xffff;
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base_hi = ((u32)(b) >> 16) & 0xff;
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base_hi2 = ((u32)(b) >> 24) & 0xff;
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}
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void set_limit(u32 l)
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{
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limit_lo = (u32)l & 0xffff;
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limit_hi = ((u32)l >> 16) & 0xf;
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}
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};
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class PageDirectoryEntry {
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public:
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const PageTableEntry* page_table_base() const { return reinterpret_cast<PageTableEntry*>(m_raw & 0xfffff000u); }
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PageTableEntry* page_table_base() { return reinterpret_cast<PageTableEntry*>(m_raw & 0xfffff000u); }
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void set_page_table_base(u32 value)
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{
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m_raw &= 0x8000000000000fffULL;
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m_raw |= value & 0xfffff000;
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}
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void clear() { m_raw = 0; }
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u64 raw() const { return m_raw; }
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void copy_from(Badge<PageDirectory>, const PageDirectoryEntry& other) { m_raw = other.m_raw; }
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enum Flags {
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Present = 1 << 0,
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ReadWrite = 1 << 1,
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UserSupervisor = 1 << 2,
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WriteThrough = 1 << 3,
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CacheDisabled = 1 << 4,
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Huge = 1 << 7,
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Global = 1 << 8,
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NoExecute = 0x8000000000000000ULL,
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};
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bool is_present() const { return raw() & Present; }
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void set_present(bool b) { set_bit(Present, b); }
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bool is_user_allowed() const { return raw() & UserSupervisor; }
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void set_user_allowed(bool b) { set_bit(UserSupervisor, b); }
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bool is_huge() const { return raw() & Huge; }
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void set_huge(bool b) { set_bit(Huge, b); }
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bool is_writable() const { return raw() & ReadWrite; }
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void set_writable(bool b) { set_bit(ReadWrite, b); }
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bool is_write_through() const { return raw() & WriteThrough; }
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void set_write_through(bool b) { set_bit(WriteThrough, b); }
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bool is_cache_disabled() const { return raw() & CacheDisabled; }
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void set_cache_disabled(bool b) { set_bit(CacheDisabled, b); }
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bool is_global() const { return raw() & Global; }
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void set_global(bool b) { set_bit(Global, b); }
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bool is_execute_disabled() const { return raw() & NoExecute; }
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void set_execute_disabled(bool b) { set_bit(NoExecute, b); }
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void set_bit(u64 bit, bool value)
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{
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if (value)
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m_raw |= bit;
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else
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m_raw &= ~bit;
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}
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private:
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u64 m_raw;
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};
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class PageTableEntry {
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public:
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void* physical_page_base() { return reinterpret_cast<void*>(m_raw & 0xfffff000u); }
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void set_physical_page_base(u32 value)
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{
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m_raw &= 0x8000000000000fffULL;
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m_raw |= value & 0xfffff000;
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}
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u64 raw() const { return (u32)m_raw; }
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enum Flags {
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Present = 1 << 0,
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ReadWrite = 1 << 1,
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UserSupervisor = 1 << 2,
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WriteThrough = 1 << 3,
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CacheDisabled = 1 << 4,
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Global = 1 << 8,
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NoExecute = 0x8000000000000000ULL,
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};
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bool is_present() const { return raw() & Present; }
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void set_present(bool b) { set_bit(Present, b); }
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bool is_user_allowed() const { return raw() & UserSupervisor; }
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void set_user_allowed(bool b) { set_bit(UserSupervisor, b); }
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bool is_writable() const { return raw() & ReadWrite; }
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void set_writable(bool b) { set_bit(ReadWrite, b); }
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bool is_write_through() const { return raw() & WriteThrough; }
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void set_write_through(bool b) { set_bit(WriteThrough, b); }
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bool is_cache_disabled() const { return raw() & CacheDisabled; }
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void set_cache_disabled(bool b) { set_bit(CacheDisabled, b); }
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bool is_global() const { return raw() & Global; }
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void set_global(bool b) { set_bit(Global, b); }
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bool is_execute_disabled() const { return raw() & NoExecute; }
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void set_execute_disabled(bool b) { set_bit(NoExecute, b); }
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void clear() { m_raw = 0; }
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void set_bit(u64 bit, bool value)
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{
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if (value)
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m_raw |= bit;
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else
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m_raw &= ~bit;
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}
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private:
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u64 m_raw;
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};
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static_assert(sizeof(PageDirectoryEntry) == 8);
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static_assert(sizeof(PageTableEntry) == 8);
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class PageDirectoryPointerTable {
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public:
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PageDirectoryEntry* directory(size_t index)
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{
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return (PageDirectoryEntry*)(raw[index] & ~0xfffu);
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}
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u64 raw[4];
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};
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class GenericInterruptHandler;
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struct RegisterState;
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const DescriptorTablePointer& get_gdtr();
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const DescriptorTablePointer& get_idtr();
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void register_interrupt_handler(u8 number, void (*f)());
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void register_user_callable_interrupt_handler(u8 number, void (*f)());
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GenericInterruptHandler& get_interrupt_handler(u8 interrupt_number);
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void register_generic_interrupt_handler(u8 number, GenericInterruptHandler&);
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void replace_single_handler_with_shared(GenericInterruptHandler&);
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void replace_shared_handler_with_single(GenericInterruptHandler&);
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void unregister_generic_interrupt_handler(u8 number, GenericInterruptHandler&);
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void flush_idt();
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void load_task_register(u16 selector);
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void handle_crash(RegisterState&, const char* description, int signal, bool out_of_memory = false);
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[[noreturn]] static inline void hang()
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{
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asm volatile("cli; hlt");
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for (;;) {
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}
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}
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#define LSW(x) ((u32)(x)&0xFFFF)
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#define MSW(x) (((u32)(x) >> 16) & 0xFFFF)
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#define LSB(x) ((x)&0xFF)
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#define MSB(x) (((x) >> 8) & 0xFF)
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#define cli() asm volatile("cli" :: \
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: "memory")
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#define sti() asm volatile("sti" :: \
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: "memory")
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#define memory_barrier() asm volatile("" :: \
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: "memory")
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inline u32 cpu_flags()
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{
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u32 flags;
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asm volatile(
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"pushf\n"
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"pop %0\n"
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: "=rm"(flags)::"memory");
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return flags;
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}
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inline void set_fs(u32 segment)
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{
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asm volatile(
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"movl %%eax, %%fs" :: "a"(segment)
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: "memory"
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);
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}
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inline void set_gs(u32 segment)
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{
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asm volatile(
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"movl %%eax, %%gs" :: "a"(segment)
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: "memory"
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);
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}
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inline u32 get_fs()
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{
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u32 fs;
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asm("mov %%fs, %%eax"
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: "=a"(fs));
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return fs;
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}
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inline u32 get_gs()
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{
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u32 gs;
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asm("mov %%gs, %%eax"
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: "=a"(gs));
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return gs;
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}
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inline u32 read_fs_u32(u32 offset)
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{
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u32 val;
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asm volatile(
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"movl %%fs:%a[off], %k[val]"
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: [ val ] "=r"(val)
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: [ off ] "ir"(offset));
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return val;
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}
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inline void write_fs_u32(u32 offset, u32 val)
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{
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asm volatile(
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"movl %k[val], %%fs:%a[off]" ::[off] "ir"(offset), [ val ] "ir"(val)
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: "memory");
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}
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inline bool are_interrupts_enabled()
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{
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return cpu_flags() & 0x200;
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}
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class InterruptFlagSaver {
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public:
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InterruptFlagSaver()
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{
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m_flags = cpu_flags();
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}
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~InterruptFlagSaver()
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{
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if (m_flags & 0x200)
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sti();
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else
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cli();
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}
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private:
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u32 m_flags;
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};
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inline bool cli_and_save_interrupt_flag()
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{
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u32 flags = cpu_flags();
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cli();
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return flags & 0x200;
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}
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inline void restore_interrupt_flag(bool flag)
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{
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if (flag)
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sti();
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else
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cli();
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}
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class InterruptDisabler {
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public:
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InterruptDisabler()
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{
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m_flags = cpu_flags();
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cli();
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}
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~InterruptDisabler()
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{
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if (m_flags & 0x200)
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sti();
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}
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private:
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u32 m_flags;
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};
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class NonMaskableInterruptDisabler {
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public:
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NonMaskableInterruptDisabler();
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~NonMaskableInterruptDisabler();
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};
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/* Map IRQ0-15 @ ISR 0x50-0x5F */
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#define IRQ_VECTOR_BASE 0x50
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struct PageFaultFlags {
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enum Flags {
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NotPresent = 0x00,
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ProtectionViolation = 0x01,
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Read = 0x00,
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Write = 0x02,
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UserMode = 0x04,
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SupervisorMode = 0x00,
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ReservedBitViolation = 0x08,
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InstructionFetch = 0x10,
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};
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};
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class PageFault {
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public:
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PageFault(u16 code, VirtualAddress vaddr)
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: m_code(code)
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, m_vaddr(vaddr)
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{
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}
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enum class Type {
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PageNotPresent = PageFaultFlags::NotPresent,
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ProtectionViolation = PageFaultFlags::ProtectionViolation,
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};
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enum class Access {
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Read = PageFaultFlags::Read,
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Write = PageFaultFlags::Write,
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};
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VirtualAddress vaddr() const { return m_vaddr; }
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u16 code() const { return m_code; }
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Type type() const { return (Type)(m_code & 1); }
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Access access() const { return (Access)(m_code & 2); }
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bool is_not_present() const { return (m_code & 1) == PageFaultFlags::NotPresent; }
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bool is_protection_violation() const { return (m_code & 1) == PageFaultFlags::ProtectionViolation; }
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bool is_read() const { return (m_code & 2) == PageFaultFlags::Read; }
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bool is_write() const { return (m_code & 2) == PageFaultFlags::Write; }
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bool is_user() const { return (m_code & 4) == PageFaultFlags::UserMode; }
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bool is_supervisor() const { return (m_code & 4) == PageFaultFlags::SupervisorMode; }
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bool is_instruction_fetch() const { return (m_code & 8) == PageFaultFlags::InstructionFetch; }
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private:
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u16 m_code;
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VirtualAddress m_vaddr;
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};
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struct [[gnu::packed]] RegisterState
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{
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u32 ss;
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u32 gs;
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u32 fs;
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u32 es;
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u32 ds;
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u32 edi;
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u32 esi;
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u32 ebp;
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u32 esp;
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u32 ebx;
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u32 edx;
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u32 ecx;
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u32 eax;
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u16 exception_code;
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u16 isr_number;
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u32 eip;
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u32 cs;
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u32 eflags;
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u32 userspace_esp;
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u32 userspace_ss;
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};
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#define REGISTER_STATE_SIZE (19 * 4)
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static_assert(REGISTER_STATE_SIZE == sizeof(RegisterState));
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struct [[gnu::aligned(16)]] FPUState
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{
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u8 buffer[512];
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};
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inline constexpr FlatPtr page_base_of(FlatPtr address)
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{
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return address & PAGE_MASK;
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}
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inline FlatPtr page_base_of(const void* address)
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{
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return page_base_of((FlatPtr)address);
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}
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inline constexpr FlatPtr offset_in_page(FlatPtr address)
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{
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return address & (~PAGE_MASK);
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}
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inline FlatPtr offset_in_page(const void* address)
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{
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return offset_in_page((FlatPtr)address);
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}
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u32 read_cr0();
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u32 read_cr3();
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void write_cr3(u32);
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u32 read_cr4();
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u32 read_dr6();
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static inline bool is_kernel_mode()
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{
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u32 cs;
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asm volatile (
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"movl %%cs, %[cs] \n"
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: [cs] "=g" (cs));
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return (cs & 3) == 0;
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}
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class CPUID {
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public:
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CPUID(u32 function) { asm volatile("cpuid"
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: "=a"(m_eax), "=b"(m_ebx), "=c"(m_ecx), "=d"(m_edx)
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: "a"(function), "c"(0)); }
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u32 eax() const { return m_eax; }
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u32 ebx() const { return m_ebx; }
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u32 ecx() const { return m_ecx; }
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u32 edx() const { return m_edx; }
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private:
|
|
u32 m_eax { 0xffffffff };
|
|
u32 m_ebx { 0xffffffff };
|
|
u32 m_ecx { 0xffffffff };
|
|
u32 m_edx { 0xffffffff };
|
|
};
|
|
|
|
inline void read_tsc(u32& lsw, u32& msw)
|
|
{
|
|
asm volatile("rdtsc"
|
|
: "=d"(msw), "=a"(lsw));
|
|
}
|
|
|
|
inline u64 read_tsc()
|
|
{
|
|
u32 lsw;
|
|
u32 msw;
|
|
read_tsc(lsw, msw);
|
|
return ((u64)msw << 32) | lsw;
|
|
}
|
|
|
|
struct Stopwatch {
|
|
union SplitQword {
|
|
struct {
|
|
uint32_t lsw;
|
|
uint32_t msw;
|
|
};
|
|
uint64_t qw { 0 };
|
|
};
|
|
|
|
public:
|
|
Stopwatch(const char* name)
|
|
: m_name(name)
|
|
{
|
|
read_tsc(m_start.lsw, m_start.msw);
|
|
}
|
|
|
|
~Stopwatch()
|
|
{
|
|
SplitQword end;
|
|
read_tsc(end.lsw, end.msw);
|
|
uint64_t diff = end.qw - m_start.qw;
|
|
dbg() << "Stopwatch(" << m_name << "): " << diff << " ticks";
|
|
}
|
|
|
|
private:
|
|
const char* m_name { nullptr };
|
|
SplitQword m_start;
|
|
};
|
|
|
|
enum class CPUFeature : u32 {
|
|
NX = (1 << 0),
|
|
PAE = (1 << 1),
|
|
PGE = (1 << 2),
|
|
RDRAND = (1 << 3),
|
|
RDSEED = (1 << 4),
|
|
SMAP = (1 << 5),
|
|
SMEP = (1 << 6),
|
|
SSE = (1 << 7),
|
|
TSC = (1 << 8),
|
|
UMIP = (1 << 9)
|
|
};
|
|
|
|
class Thread;
|
|
struct TrapFrame;
|
|
|
|
#define GDT_SELECTOR_CODE0 0x08
|
|
#define GDT_SELECTOR_DATA0 0x10
|
|
#define GDT_SELECTOR_CODE3 0x18
|
|
#define GDT_SELECTOR_DATA3 0x20
|
|
#define GDT_SELECTOR_TLS 0x28
|
|
#define GDT_SELECTOR_PROC 0x30
|
|
#define GDT_SELECTOR_TSS 0x38
|
|
|
|
class ProcessorInfo;
|
|
struct MemoryManagerData;
|
|
|
|
class Processor {
|
|
friend class ProcessorInfo;
|
|
|
|
Processor* m_self; // must be first field (%fs offset 0x0)
|
|
|
|
DescriptorTablePointer m_gdtr;
|
|
Descriptor m_gdt[256];
|
|
u32 m_gdt_length;
|
|
|
|
u32 m_cpu;
|
|
u32 m_in_irq;
|
|
u32 m_in_critical;
|
|
|
|
TSS32 m_tss;
|
|
static FPUState s_clean_fpu_state;
|
|
CPUFeature m_features;
|
|
|
|
ProcessorInfo* m_info;
|
|
MemoryManagerData* m_mm_data;
|
|
Thread* m_current_thread;
|
|
Thread* m_idle_thread;
|
|
|
|
bool m_invoke_scheduler_async;
|
|
bool m_scheduler_initialized;
|
|
|
|
void gdt_init();
|
|
void write_raw_gdt_entry(u16 selector, u32 low, u32 high);
|
|
void write_gdt_entry(u16 selector, Descriptor& descriptor);
|
|
static Vector<Processor*>& processors();
|
|
|
|
void cpu_detect();
|
|
void cpu_setup();
|
|
|
|
String features_string() const;
|
|
|
|
public:
|
|
void early_initialize(u32 cpu);
|
|
void initialize(u32 cpu);
|
|
|
|
Descriptor& get_gdt_entry(u16 selector);
|
|
void flush_gdt();
|
|
const DescriptorTablePointer& get_gdtr();
|
|
|
|
static Processor& by_id(u32 cpu);
|
|
|
|
template <typename Callback>
|
|
static inline IterationDecision for_each(Callback callback)
|
|
{
|
|
auto& procs = processors();
|
|
for (auto it = procs.begin(); it != procs.end(); ++it) {
|
|
if (callback(**it) == IterationDecision::Break)
|
|
return IterationDecision::Break;
|
|
}
|
|
return IterationDecision::Continue;
|
|
}
|
|
|
|
ALWAYS_INLINE ProcessorInfo& info() { return *m_info; }
|
|
|
|
ALWAYS_INLINE static Processor& current()
|
|
{
|
|
return *(Processor*)read_fs_u32(0);
|
|
}
|
|
|
|
ALWAYS_INLINE static bool is_initialized()
|
|
{
|
|
return get_fs() == GDT_SELECTOR_PROC && read_fs_u32(0) != 0;
|
|
}
|
|
|
|
ALWAYS_INLINE void set_mm_data(MemoryManagerData& mm_data)
|
|
{
|
|
m_mm_data = &mm_data;
|
|
}
|
|
|
|
ALWAYS_INLINE MemoryManagerData& get_mm_data() const
|
|
{
|
|
return *m_mm_data;
|
|
}
|
|
|
|
ALWAYS_INLINE Thread* idle_thread() const
|
|
{
|
|
return m_idle_thread;
|
|
}
|
|
|
|
ALWAYS_INLINE void set_idle_thread(Thread& idle_thread)
|
|
{
|
|
m_idle_thread = &idle_thread;
|
|
}
|
|
|
|
ALWAYS_INLINE Thread* current_thread() const
|
|
{
|
|
// NOTE: NOT safe to call from another processor!
|
|
ASSERT(&Processor::current() == this);
|
|
return m_current_thread;
|
|
}
|
|
|
|
ALWAYS_INLINE void set_current_thread(Thread& current_thread)
|
|
{
|
|
m_current_thread = ¤t_thread;
|
|
}
|
|
|
|
ALWAYS_INLINE u32 id()
|
|
{
|
|
return m_cpu;
|
|
}
|
|
|
|
ALWAYS_INLINE u32& in_irq()
|
|
{
|
|
return m_in_irq;
|
|
}
|
|
|
|
ALWAYS_INLINE void enter_critical(u32& prev_flags)
|
|
{
|
|
m_in_critical++;
|
|
prev_flags = cpu_flags();
|
|
cli();
|
|
}
|
|
|
|
ALWAYS_INLINE void leave_critical(u32 prev_flags)
|
|
{
|
|
ASSERT(m_in_critical > 0);
|
|
if (--m_in_critical == 0) {
|
|
if (!m_in_irq)
|
|
check_invoke_scheduler();
|
|
}
|
|
if (prev_flags & 0x200)
|
|
sti();
|
|
}
|
|
|
|
ALWAYS_INLINE u32& in_critical() { return m_in_critical; }
|
|
|
|
ALWAYS_INLINE const FPUState& clean_fpu_state() const
|
|
{
|
|
return s_clean_fpu_state;
|
|
}
|
|
|
|
ALWAYS_INLINE bool has_feature(CPUFeature f) const
|
|
{
|
|
return (static_cast<u32>(m_features) & static_cast<u32>(f)) != 0;
|
|
}
|
|
|
|
void check_invoke_scheduler();
|
|
void invoke_scheduler_async() { m_invoke_scheduler_async = true; }
|
|
|
|
void enter_trap(TrapFrame& trap, bool raise_irq);
|
|
void exit_trap(TrapFrame& trap);
|
|
|
|
[[noreturn]] void initialize_context_switching(Thread& initial_thread);
|
|
void switch_context(Thread* from_thread, Thread* to_thread);
|
|
[[noreturn]] static void assume_context(Thread& thread, u32 flags);
|
|
u32 init_context(Thread& thread, bool leave_crit);
|
|
|
|
void set_thread_specific(u8* data, size_t len);
|
|
};
|
|
|
|
class ScopedCritical
|
|
{
|
|
u32 m_prev_flags;
|
|
bool m_valid;
|
|
|
|
public:
|
|
ScopedCritical(const ScopedCritical&) = delete;
|
|
ScopedCritical& operator=(const ScopedCritical&) = delete;
|
|
|
|
ScopedCritical()
|
|
{
|
|
m_valid = true;
|
|
Processor::current().enter_critical(m_prev_flags);
|
|
}
|
|
|
|
~ScopedCritical()
|
|
{
|
|
if (m_valid) {
|
|
m_valid = false;
|
|
Processor::current().leave_critical(m_prev_flags);
|
|
}
|
|
}
|
|
|
|
ScopedCritical(ScopedCritical&& from):
|
|
m_prev_flags(from.m_prev_flags),
|
|
m_valid(from.m_valid)
|
|
{
|
|
from.m_prev_flags = 0;
|
|
from.m_valid = false;
|
|
}
|
|
|
|
ScopedCritical& operator=(ScopedCritical&& from)
|
|
{
|
|
if (&from != this) {
|
|
m_prev_flags = from.m_prev_flags;
|
|
m_valid = from.m_valid;
|
|
from.m_prev_flags = 0;
|
|
from.m_valid = false;
|
|
}
|
|
return *this;
|
|
}
|
|
};
|
|
|
|
struct TrapFrame {
|
|
u32 prev_irq_level;
|
|
RegisterState* regs; // must be last
|
|
|
|
TrapFrame() = delete;
|
|
TrapFrame(const TrapFrame&) = delete;
|
|
TrapFrame(TrapFrame&&) = delete;
|
|
TrapFrame& operator=(const TrapFrame&) = delete;
|
|
TrapFrame& operator=(TrapFrame&&) = delete;
|
|
};
|
|
|
|
#define TRAP_FRAME_SIZE (2 * 4)
|
|
static_assert(TRAP_FRAME_SIZE == sizeof(TrapFrame));
|
|
|
|
extern "C" void enter_trap_no_irq(TrapFrame*);
|
|
extern "C" void enter_trap(TrapFrame*);
|
|
extern "C" void exit_trap(TrapFrame*);
|
|
|
|
class MSR {
|
|
uint32_t m_msr;
|
|
|
|
public:
|
|
static bool have()
|
|
{
|
|
CPUID id(1);
|
|
return (id.edx() & (1 << 5)) != 0;
|
|
}
|
|
|
|
MSR(const MSR&) = delete;
|
|
MSR& operator=(const MSR&) = delete;
|
|
|
|
MSR(uint32_t msr)
|
|
: m_msr(msr)
|
|
{
|
|
}
|
|
|
|
void get(u32& low, u32& high)
|
|
{
|
|
asm volatile("rdmsr"
|
|
: "=a"(low), "=d"(high)
|
|
: "c"(m_msr));
|
|
}
|
|
|
|
void set(u32 low, u32 high)
|
|
{
|
|
asm volatile("wrmsr" ::"a"(low), "d"(high), "c"(m_msr));
|
|
}
|
|
};
|
|
|
|
ALWAYS_INLINE void stac()
|
|
{
|
|
if (!Processor::current().has_feature(CPUFeature::SMAP))
|
|
return;
|
|
asm volatile("stac" ::
|
|
: "cc");
|
|
}
|
|
|
|
ALWAYS_INLINE void clac()
|
|
{
|
|
if (!Processor::current().has_feature(CPUFeature::SMAP))
|
|
return;
|
|
asm volatile("clac" ::
|
|
: "cc");
|
|
}
|
|
|
|
class SmapDisabler {
|
|
public:
|
|
ALWAYS_INLINE SmapDisabler()
|
|
{
|
|
m_flags = cpu_flags();
|
|
stac();
|
|
}
|
|
|
|
ALWAYS_INLINE ~SmapDisabler()
|
|
{
|
|
if (!(m_flags & 0x40000))
|
|
clac();
|
|
}
|
|
|
|
private:
|
|
u32 m_flags;
|
|
};
|
|
|
|
}
|