mirror of
https://github.com/RGBCube/serenity
synced 2025-06-17 08:12:06 +00:00
57901a6f62
This initial implementation flushes the complete tlb cache. A FIXME is added to implement the partial tlb flushing.
56 lines
1.3 KiB
C++
56 lines
1.3 KiB
C++
/*
|
|
* Copyright (c) 2022, Timon Kruiper <timonkruiper@gmail.com>
|
|
*
|
|
* SPDX-License-Identifier: BSD-2-Clause
|
|
*/
|
|
|
|
#include <AK/Format.h>
|
|
|
|
#include <Kernel/Arch/Processor.h>
|
|
#include <Kernel/Arch/aarch64/ASM_wrapper.h>
|
|
#include <Kernel/Arch/aarch64/CPU.h>
|
|
|
|
extern "C" uintptr_t vector_table_el1;
|
|
|
|
namespace Kernel {
|
|
|
|
Processor* g_current_processor;
|
|
|
|
void Processor::initialize(u32 cpu)
|
|
{
|
|
VERIFY(g_current_processor == nullptr);
|
|
|
|
auto current_exception_level = static_cast<u64>(Aarch64::Asm::get_current_exception_level());
|
|
dbgln("CPU{} started in: EL{}", cpu, current_exception_level);
|
|
|
|
dbgln("Drop CPU{} to EL1", cpu);
|
|
drop_to_exception_level_1();
|
|
|
|
// Load EL1 vector table
|
|
Aarch64::Asm::el1_vector_table_install(&vector_table_el1);
|
|
|
|
g_current_processor = this;
|
|
}
|
|
|
|
[[noreturn]] void Processor::halt()
|
|
{
|
|
disable_interrupts();
|
|
for (;;)
|
|
asm volatile("wfi");
|
|
}
|
|
|
|
void Processor::flush_tlb_local(VirtualAddress, size_t)
|
|
{
|
|
// FIXME: Figure out how to flush a single page
|
|
asm volatile("dsb ishst");
|
|
asm volatile("tlbi vmalle1is");
|
|
asm volatile("dsb ish");
|
|
asm volatile("isb");
|
|
}
|
|
|
|
void Processor::flush_tlb(Memory::PageDirectory const*, VirtualAddress vaddr, size_t page_count)
|
|
{
|
|
flush_tlb_local(vaddr, page_count);
|
|
}
|
|
|
|
}
|