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https://github.com/RGBCube/serenity
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ac2c01320b
Two classes are added - HostBridge and MemoryBackedHostBridge, which both derive from HostController class. This allows the kernel to map different busses from different PCI domains in the same time. Each HostController implementation doesn't take the Address object to address PCI devices but instead we take distinct numbers of the PCI bus, device and function as it allows us to specify arbitrary PCI domains in the Address structure and still to get the correct PCI devices. This also matches the hardware behavior of PCI domains - the host bridge merely takes memory operations or IO operations and translates them to addressing of three components - PCI bus, device and function. These changes also greatly simplify how enumeration of Host Bridges work now - scanning of the hardware depends on what the Host bridges can do for us, so in case we have multiple host bridges that expose a memory mapped region or IO ports to access PCI configuration space, we simply let the code of the host bridge to figure out how to fetch data for us. Another semantical change is that a PCI domain structure is no longer attached to a PhysicalAddress, so even in the case that the machine doesn't implement PCI domains, we still treat that machine to contain 1 PCI domain to treat that one host bridge in the same way, like with a machine with one or more PCI domains.
79 lines
2 KiB
C++
79 lines
2 KiB
C++
/*
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* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <Kernel/Arch/x86/IO.h>
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#include <Kernel/Bus/PCI/API.h>
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#include <Kernel/Bus/PCI/Access.h>
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#include <Kernel/Bus/PCI/Initializer.h>
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#include <Kernel/Bus/PCI/SysFSPCI.h>
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#include <Kernel/CommandLine.h>
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#include <Kernel/Firmware/ACPI/Parser.h>
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#include <Kernel/Panic.h>
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#include <Kernel/Sections.h>
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namespace Kernel {
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namespace PCI {
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static bool test_pci_io();
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UNMAP_AFTER_INIT static PCIAccessLevel detect_optimal_access_type()
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{
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auto boot_determined = kernel_command_line().pci_access_level();
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if (!ACPI::is_enabled() || !ACPI::Parser::the()->find_table("MCFG").has_value())
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return PCIAccessLevel::IOAddressing;
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if (boot_determined != PCIAccessLevel::IOAddressing)
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return boot_determined;
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if (test_pci_io())
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return PCIAccessLevel::IOAddressing;
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PANIC("No PCI bus access method detected!");
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}
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UNMAP_AFTER_INIT void initialize()
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{
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switch (detect_optimal_access_type()) {
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case PCIAccessLevel::MemoryAddressing: {
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auto mcfg = ACPI::Parser::the()->find_table("MCFG");
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VERIFY(mcfg.has_value());
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auto success = Access::initialize_for_multiple_pci_domains(mcfg.value());
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VERIFY(success);
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break;
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}
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case PCIAccessLevel::IOAddressing: {
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auto success = Access::initialize_for_one_pci_domain();
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VERIFY(success);
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break;
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}
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default:
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VERIFY_NOT_REACHED();
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}
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PCI::PCIBusSysFSDirectory::initialize();
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PCI::enumerate([&](DeviceIdentifier const& device_identifier) {
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dmesgln("{} {}", device_identifier.address(), device_identifier.hardware_id());
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});
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}
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UNMAP_AFTER_INIT bool test_pci_io()
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{
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dmesgln("Testing PCI via manual probing...");
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u32 tmp = 0x80000000;
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IO::out32(PCI::address_port, tmp);
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tmp = IO::in32(PCI::address_port);
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if (tmp == 0x80000000) {
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dmesgln("PCI IO supported");
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return true;
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}
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dmesgln("PCI IO not supported");
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return false;
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}
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}
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}
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