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bfcf7ab3e8
This is in preparation for adding MSI(x) support to the NVMe device. NVMeInterruptQueue needs access to the PCI device to deal with MSI(x) interrupts. It is ok to pass the NVMeController as a reference to the NVMeQueue as NVMeController is the one that owns the NVMeQueue. This is very similar to how AHCIController passes its reference to its interrupt handler.
24 lines
917 B
C++
24 lines
917 B
C++
/*
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* Copyright (c) 2022, Pankaj R <pankydev8@gmail.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <Kernel/Storage/NVMe/NVMeQueue.h>
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namespace Kernel {
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class NVMeInterruptQueue : public NVMeQueue
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, public IRQHandler {
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public:
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NVMeInterruptQueue(PCI::Device& device, NonnullOwnPtr<Memory::Region> rw_dma_region, Memory::PhysicalPage const& rw_dma_page, u16 qid, u8 irq, u32 q_depth, OwnPtr<Memory::Region> cq_dma_region, Vector<NonnullRefPtr<Memory::PhysicalPage>> cq_dma_page, OwnPtr<Memory::Region> sq_dma_region, Vector<NonnullRefPtr<Memory::PhysicalPage>> sq_dma_page, Memory::TypedMapping<DoorbellRegister volatile> db_regs);
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void submit_sqe(NVMeSubmission& submission) override;
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virtual ~NVMeInterruptQueue() override {};
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private:
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virtual void complete_current_request(u16 cmdid, u16 status) override;
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bool handle_irq(RegisterState const&) override;
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};
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}
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