mirror of
https://github.com/RGBCube/serenity
synced 2025-10-31 10:52:44 +00:00
100 lines
3.4 KiB
C++
100 lines
3.4 KiB
C++
/*
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* Copyright (c) 2020, Andreas Kling <kling@serenityos.org>
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* Copyright (c) 2020-2021, Jesse Buhagiar <jooster669@gmail.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/Platform.h>
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#include <AK/NonnullOwnPtr.h>
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#include <Kernel/Bus/PCI/Device.h>
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#include <Kernel/Bus/USB/UHCIDescriptorTypes.h>
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#include <Kernel/Bus/USB/USBDevice.h>
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#include <Kernel/Bus/USB/USBTransfer.h>
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#include <Kernel/IO.h>
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#include <Kernel/Memory/AnonymousVMObject.h>
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#include <Kernel/Process.h>
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#include <Kernel/Time/TimeManagement.h>
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namespace Kernel::USB {
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class UHCIController final : public PCI::Device {
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public:
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static void detect();
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static UHCIController& the();
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virtual ~UHCIController() override;
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virtual StringView purpose() const override { return "UHCI"; }
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void reset();
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void stop();
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void start();
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void spawn_port_proc();
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void do_debug_transfer();
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KResultOr<size_t> submit_control_transfer(Transfer& transfer);
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RefPtr<USB::Device> const get_device_at_port(USB::Device::PortNumber);
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RefPtr<USB::Device> const get_device_from_address(u8 device_address);
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private:
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UHCIController(PCI::Address, PCI::ID);
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u16 read_usbcmd() { return m_io_base.offset(0).in<u16>(); }
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u16 read_usbsts() { return m_io_base.offset(0x2).in<u16>(); }
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u16 read_usbintr() { return m_io_base.offset(0x4).in<u16>(); }
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u16 read_frnum() { return m_io_base.offset(0x6).in<u16>(); }
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u32 read_flbaseadd() { return m_io_base.offset(0x8).in<u32>(); }
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u8 read_sofmod() { return m_io_base.offset(0xc).in<u8>(); }
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u16 read_portsc1() { return m_io_base.offset(0x10).in<u16>(); }
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u16 read_portsc2() { return m_io_base.offset(0x12).in<u16>(); }
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void write_usbcmd(u16 value) { m_io_base.offset(0).out(value); }
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void write_usbsts(u16 value) { m_io_base.offset(0x2).out(value); }
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void write_usbintr(u16 value) { m_io_base.offset(0x4).out(value); }
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void write_frnum(u16 value) { m_io_base.offset(0x6).out(value); }
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void write_flbaseadd(u32 value) { m_io_base.offset(0x8).out(value); }
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void write_sofmod(u8 value) { m_io_base.offset(0xc).out(value); }
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void write_portsc1(u16 value) { m_io_base.offset(0x10).out(value); }
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void write_portsc2(u16 value) { m_io_base.offset(0x12).out(value); }
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virtual bool handle_irq(const RegisterState&) override;
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void create_structures();
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void setup_schedule();
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size_t poll_transfer_queue(QueueHead& transfer_queue);
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TransferDescriptor* create_transfer_descriptor(Pipe& pipe, PacketID direction, size_t data_len);
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KResult create_chain(Pipe& pipe, PacketID direction, Ptr32<u8>& buffer_address, size_t max_size, size_t transfer_size, TransferDescriptor** td_chain, TransferDescriptor** last_td);
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void free_descriptor_chain(TransferDescriptor* first_descriptor);
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QueueHead* allocate_queue_head() const;
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TransferDescriptor* allocate_transfer_descriptor() const;
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private:
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IOAddress m_io_base;
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Vector<QueueHead*> m_free_qh_pool;
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Vector<TransferDescriptor*> m_free_td_pool;
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Vector<TransferDescriptor*> m_iso_td_list;
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QueueHead* m_interrupt_transfer_queue;
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QueueHead* m_lowspeed_control_qh;
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QueueHead* m_fullspeed_control_qh;
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QueueHead* m_bulk_qh;
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QueueHead* m_dummy_qh; // Needed for PIIX4 hack
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OwnPtr<Memory::Region> m_framelist;
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OwnPtr<Memory::Region> m_qh_pool;
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OwnPtr<Memory::Region> m_td_pool;
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Array<RefPtr<USB::Device>, 2> m_devices; // Devices connected to the root ports (of which there are two)
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};
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}
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