mirror of
https://github.com/RGBCube/serenity
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79fa9765ca
We now use AK::Error and AK::ErrorOr<T> in both kernel and userspace! This was a slightly tedious refactoring that took a long time, so it's not unlikely that some bugs crept in. Nevertheless, it does pass basic functionality testing, and it's just real nice to finally see the same pattern in all contexts. :^)
114 lines
4.4 KiB
C++
114 lines
4.4 KiB
C++
/*
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* Copyright (c) 2020, Andreas Kling <kling@serenityos.org>
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* Copyright (c) 2020-2021, Jesse Buhagiar <jooster669@gmail.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/Platform.h>
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#include <AK/NonnullOwnPtr.h>
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#include <Kernel/Arch/x86/IO.h>
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#include <Kernel/Bus/PCI/Device.h>
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#include <Kernel/Bus/USB/UHCI/UHCIDescriptorPool.h>
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#include <Kernel/Bus/USB/UHCI/UHCIDescriptorTypes.h>
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#include <Kernel/Bus/USB/UHCI/UHCIRootHub.h>
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#include <Kernel/Bus/USB/USBController.h>
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#include <Kernel/Interrupts/IRQHandler.h>
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#include <Kernel/Memory/AnonymousVMObject.h>
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#include <Kernel/Process.h>
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#include <Kernel/Time/TimeManagement.h>
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namespace Kernel::USB {
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class UHCIController final
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: public USBController
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, public PCI::Device
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, public IRQHandler {
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static constexpr u8 MAXIMUM_NUMBER_OF_TDS = 128; // Upper pool limit. This consumes the second page we have allocated
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static constexpr u8 MAXIMUM_NUMBER_OF_QHS = 64;
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public:
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static constexpr u8 NUMBER_OF_ROOT_PORTS = 2;
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static ErrorOr<NonnullRefPtr<UHCIController>> try_to_initialize(PCI::DeviceIdentifier const& pci_device_identifier);
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virtual ~UHCIController() override;
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virtual StringView purpose() const override { return "UHCI"sv; }
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virtual ErrorOr<void> initialize() override;
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virtual ErrorOr<void> reset() override;
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virtual ErrorOr<void> stop() override;
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virtual ErrorOr<void> start() override;
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void spawn_port_proc();
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void do_debug_transfer();
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virtual ErrorOr<size_t> submit_control_transfer(Transfer& transfer) override;
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void get_port_status(Badge<UHCIRootHub>, u8, HubStatus&);
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ErrorOr<void> set_port_feature(Badge<UHCIRootHub>, u8, HubFeatureSelector);
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ErrorOr<void> clear_port_feature(Badge<UHCIRootHub>, u8, HubFeatureSelector);
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private:
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explicit UHCIController(PCI::DeviceIdentifier const& pci_device_identifier);
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u16 read_usbcmd() { return m_io_base.offset(0).in<u16>(); }
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u16 read_usbsts() { return m_io_base.offset(0x2).in<u16>(); }
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u16 read_usbintr() { return m_io_base.offset(0x4).in<u16>(); }
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u16 read_frnum() { return m_io_base.offset(0x6).in<u16>(); }
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u32 read_flbaseadd() { return m_io_base.offset(0x8).in<u32>(); }
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u8 read_sofmod() { return m_io_base.offset(0xc).in<u8>(); }
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u16 read_portsc1() { return m_io_base.offset(0x10).in<u16>(); }
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u16 read_portsc2() { return m_io_base.offset(0x12).in<u16>(); }
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void write_usbcmd(u16 value) { m_io_base.offset(0).out(value); }
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void write_usbsts(u16 value) { m_io_base.offset(0x2).out(value); }
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void write_usbintr(u16 value) { m_io_base.offset(0x4).out(value); }
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void write_frnum(u16 value) { m_io_base.offset(0x6).out(value); }
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void write_flbaseadd(u32 value) { m_io_base.offset(0x8).out(value); }
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void write_sofmod(u8 value) { m_io_base.offset(0xc).out(value); }
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void write_portsc1(u16 value) { m_io_base.offset(0x10).out(value); }
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void write_portsc2(u16 value) { m_io_base.offset(0x12).out(value); }
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virtual bool handle_irq(const RegisterState&) override;
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ErrorOr<void> create_structures();
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void setup_schedule();
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size_t poll_transfer_queue(QueueHead& transfer_queue);
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TransferDescriptor* create_transfer_descriptor(Pipe& pipe, PacketID direction, size_t data_len);
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ErrorOr<void> create_chain(Pipe& pipe, PacketID direction, Ptr32<u8>& buffer_address, size_t max_size, size_t transfer_size, TransferDescriptor** td_chain, TransferDescriptor** last_td);
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void free_descriptor_chain(TransferDescriptor* first_descriptor);
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QueueHead* allocate_queue_head();
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TransferDescriptor* allocate_transfer_descriptor();
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void reset_port(u8);
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private:
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IOAddress m_io_base;
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OwnPtr<UHCIRootHub> m_root_hub;
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OwnPtr<UHCIDescriptorPool<QueueHead>> m_queue_head_pool;
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OwnPtr<UHCIDescriptorPool<TransferDescriptor>> m_transfer_descriptor_pool;
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Vector<TransferDescriptor*> m_iso_td_list;
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QueueHead* m_interrupt_transfer_queue;
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QueueHead* m_lowspeed_control_qh;
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QueueHead* m_fullspeed_control_qh;
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QueueHead* m_bulk_qh;
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QueueHead* m_dummy_qh; // Needed for PIIX4 hack
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OwnPtr<Memory::Region> m_framelist;
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OwnPtr<Memory::Region> m_isochronous_transfer_pool;
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// Bitfield containing whether a given port should signal a change in reset or not.
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u8 m_port_reset_change_statuses { 0 };
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// Bitfield containing whether a given port should signal a change in suspend or not.
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u8 m_port_suspend_change_statuses { 0 };
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};
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}
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