mirror of
https://github.com/RGBCube/serenity
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e99fafb683
Add a basic NVMe driver support to serenity based on NVMe spec 1.4. The driver can support multiple NVMe drives (subsystems). But in a NVMe drive, the driver can support one controller with multiple namespaces. Each core will get a separate NVMe Queue. As the system lacks MSI support, PIN based interrupts are used for IO. Tested the NVMe support by replacing IDE driver with the NVMe driver :^)
79 lines
2.3 KiB
C++
79 lines
2.3 KiB
C++
/*
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* Copyright (c) 2021, Pankaj R <pankydev8@gmail.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/NonnullRefPtr.h>
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#include <AK/NonnullRefPtrVector.h>
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#include <AK/OwnPtr.h>
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#include <AK/RefPtr.h>
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#include <AK/Tuple.h>
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#include <AK/Types.h>
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#include <Kernel/Bus/PCI/Device.h>
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#include <Kernel/Locking/Spinlock.h>
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#include <Kernel/Memory/TypedMapping.h>
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#include <Kernel/Storage/NVMe/NVMeDefinitions.h>
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#include <Kernel/Storage/NVMe/NVMeNameSpace.h>
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#include <Kernel/Storage/NVMe/NVMeQueue.h>
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#include <Kernel/Storage/StorageController.h>
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namespace Kernel {
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class NVMeController : public PCI::Device
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, public StorageController {
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public:
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static ErrorOr<NonnullRefPtr<NVMeController>> try_initialize(PCI::DeviceIdentifier const&);
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ErrorOr<void> initialize();
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explicit NVMeController(PCI::DeviceIdentifier const&);
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RefPtr<StorageDevice> device(u32 index) const override;
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size_t devices_count() const override;
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protected:
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bool reset() override;
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bool shutdown() override;
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void complete_current_request(AsyncDeviceRequest::RequestResult result) override;
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public:
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bool reset_controller();
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bool start_controller();
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u32 get_admin_q_dept();
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u16 submit_admin_command(struct NVMeSubmission& sub, bool sync = false)
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{
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// First queue is always the admin queue
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if (sync) {
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return m_admin_queue->submit_sync_sqe(sub);
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}
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m_admin_queue->submit_sqe(sub);
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return 0;
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}
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bool is_admin_queue_ready() { return m_admin_queue_ready; };
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void set_admin_queue_ready_flag() { m_admin_queue_ready = true; };
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private:
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ErrorOr<void> identify_and_init_namespaces();
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Tuple<u64, u8> get_ns_features(IdentifyNamespace& identify_data_struct);
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ErrorOr<void> create_admin_queue(u8 irq);
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ErrorOr<void> create_io_queue(u8 irq, u8 qid);
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void calculate_doorbell_stride()
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{
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m_dbl_stride = (m_controller_regs->cap >> CAP_DBL_SHIFT) & CAP_DBL_MASK;
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}
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private:
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PCI::DeviceIdentifier m_pci_device_id;
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RefPtr<NVMeQueue> m_admin_queue;
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NonnullRefPtrVector<NVMeQueue> m_queues;
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NonnullRefPtrVector<NVMeNameSpace> m_namespaces;
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Memory::TypedMapping<ControllerRegister> m_controller_regs;
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bool m_admin_queue_ready { false };
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size_t m_device_count {};
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u32 m_bar;
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u8 m_dbl_stride;
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static Atomic<u8> controller_id;
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};
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}
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