mirror of
https://github.com/RGBCube/serenity
synced 2025-05-25 19:05:07 +00:00
424 lines
11 KiB
C++
424 lines
11 KiB
C++
#include "IDEDiskDevice.h"
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#include <AK/Types.h>
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#include "Process.h"
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#include "StdLib.h"
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#include "IO.h"
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#include "Scheduler.h"
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#include "PIC.h"
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#include <Kernel/Lock.h>
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//#define DISK_DEBUG
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#define IRQ_FIXED_DISK 14
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#define IDE0_DATA 0x1F0
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#define IDE0_STATUS 0x1F7
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#define IDE0_COMMAND 0x1F7
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#define ATA_SR_BSY 0x80
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#define ATA_SR_DRDY 0x40
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#define ATA_SR_DF 0x20
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#define ATA_SR_DSC 0x10
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#define ATA_SR_DRQ 0x08
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#define ATA_SR_CORR 0x04
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#define ATA_SR_IDX 0x02
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#define ATA_SR_ERR 0x01
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#define ATA_ER_BBK 0x80
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#define ATA_ER_UNC 0x40
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#define ATA_ER_MC 0x20
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#define ATA_ER_IDNF 0x10
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#define ATA_ER_MCR 0x08
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#define ATA_ER_ABRT 0x04
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#define ATA_ER_TK0NF 0x02
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#define ATA_ER_AMNF 0x01
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#define ATA_CMD_READ_PIO 0x20
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#define ATA_CMD_READ_PIO_EXT 0x24
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#define ATA_CMD_READ_DMA 0xC8
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#define ATA_CMD_READ_DMA_EXT 0x25
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#define ATA_CMD_WRITE_PIO 0x30
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#define ATA_CMD_WRITE_PIO_EXT 0x34
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#define ATA_CMD_WRITE_DMA 0xCA
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#define ATA_CMD_WRITE_DMA_EXT 0x35
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#define ATA_CMD_CACHE_FLUSH 0xE7
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#define ATA_CMD_CACHE_FLUSH_EXT 0xEA
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#define ATA_CMD_PACKET 0xA0
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#define ATA_CMD_IDENTIFY_PACKET 0xA1
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#define ATA_CMD_IDENTIFY 0xEC
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#define ATAPI_CMD_READ 0xA8
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#define ATAPI_CMD_EJECT 0x1B
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#define ATA_IDENT_DEVICETYPE 0
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#define ATA_IDENT_CYLINDERS 2
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#define ATA_IDENT_HEADS 6
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#define ATA_IDENT_SECTORS 12
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#define ATA_IDENT_SERIAL 20
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#define ATA_IDENT_MODEL 54
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#define ATA_IDENT_CAPABILITIES 98
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#define ATA_IDENT_FIELDVALID 106
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#define ATA_IDENT_MAX_LBA 120
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#define ATA_IDENT_COMMANDSETS 164
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#define ATA_IDENT_MAX_LBA_EXT 200
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#define IDE_ATA 0x00
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#define IDE_ATAPI 0x01
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#define ATA_REG_DATA 0x00
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#define ATA_REG_ERROR 0x01
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#define ATA_REG_FEATURES 0x01
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#define ATA_REG_SECCOUNT0 0x02
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#define ATA_REG_LBA0 0x03
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#define ATA_REG_LBA1 0x04
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#define ATA_REG_LBA2 0x05
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#define ATA_REG_HDDEVSEL 0x06
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#define ATA_REG_COMMAND 0x07
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#define ATA_REG_STATUS 0x07
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#define ATA_REG_SECCOUNT1 0x08
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#define ATA_REG_LBA3 0x09
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#define ATA_REG_LBA4 0x0A
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#define ATA_REG_LBA5 0x0B
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#define ATA_REG_CONTROL 0x0C
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#define ATA_REG_ALTSTATUS 0x0C
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#define ATA_REG_DEVADDRESS 0x0D
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enum IDECommand : byte {
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IDENTIFY_DRIVE = 0xEC,
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READ_SECTORS = 0x21,
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WRITE_SECTORS = 0x30,
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FLUSH_CACHE = 0xe7,
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};
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enum IDEStatus : byte {
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BUSY = (1 << 7),
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DRDY = (1 << 6),
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DF = (1 << 5),
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SRV = (1 << 4),
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DRQ = (1 << 3),
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CORR = (1 << 2),
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IDX = (1 << 1),
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ERR = (1 << 0),
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};
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Retained<IDEDiskDevice> IDEDiskDevice::create()
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{
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return adopt(*new IDEDiskDevice);
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}
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IDEDiskDevice::IDEDiskDevice()
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: IRQHandler(IRQ_FIXED_DISK)
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{
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initialize();
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}
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IDEDiskDevice::~IDEDiskDevice()
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{
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}
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const char* IDEDiskDevice::class_name() const
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{
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return "IDEDiskDevice";
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}
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unsigned IDEDiskDevice::block_size() const
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{
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return 512;
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}
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bool IDEDiskDevice::read_block(unsigned index, byte* out) const
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{
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if (m_bus_master_base)
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return const_cast<IDEDiskDevice&>(*this).read_sector_with_dma(index, out);
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return const_cast<IDEDiskDevice&>(*this).read_sectors(index, 1, out);
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}
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bool IDEDiskDevice::write_block(unsigned index, const byte* data)
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{
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return write_sectors(index, 1, data);
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}
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static void print_ide_status(byte status)
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{
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kprintf("DRQ=%u BUSY=%u DRDY=%u SRV=%u DF=%u CORR=%u IDX=%u ERR=%u\n",
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(status & DRQ) != 0,
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(status & BUSY) != 0,
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(status & DRDY) != 0,
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(status & SRV) != 0,
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(status & DF) != 0,
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(status & CORR) != 0,
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(status & IDX) != 0,
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(status & ERR) != 0);
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}
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bool IDEDiskDevice::wait_for_irq()
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{
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#ifdef DISK_DEBUG
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kprintf("disk: waiting for interrupt...\n");
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#endif
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// FIXME: Add timeout.
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while (!m_interrupted) {
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// FIXME: Put this process into a Blocked state instead, it's stupid to wake up just to check a flag.
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Scheduler::yield();
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}
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#ifdef DISK_DEBUG
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kprintf("disk: got interrupt!\n");
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#endif
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memory_barrier();
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return true;
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}
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void IDEDiskDevice::handle_irq()
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{
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byte status = IO::in8(0x1f7);
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if (status & ERR) {
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print_ide_status(status);
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m_device_error = IO::in8(0x1f1);
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kprintf("IDEDiskDevice: Error %b!\n", m_device_error);
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} else {
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m_device_error = 0;
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}
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#ifdef DISK_DEBUG
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kprintf("disk:interrupt: DRQ=%u BUSY=%u DRDY=%u\n", (status & DRQ) != 0, (status & BUSY) != 0, (status & DRDY) != 0);
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#endif
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m_interrupted = true;
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}
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void IDEDiskDevice::initialize()
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{
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static const PCI::ID piix3_ide_id = { 0x8086, 0x7010 };
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static const PCI::ID piix4_ide_id = { 0x8086, 0x7111 };
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PCI::enumerate_all([this] (const PCI::Address& address, PCI::ID id) {
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if (id == piix3_ide_id || id == piix4_ide_id) {
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m_pci_address = address;
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kprintf("PIIX%u IDE device found!\n", id == piix3_ide_id ? 3 : 4);
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}
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});
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#ifdef DISK_DEBUG
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byte status = IO::in8(IDE0_STATUS);
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kprintf("initial status: ");
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print_ide_status(status);
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#endif
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m_interrupted = false;
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while (IO::in8(IDE0_STATUS) & BUSY);
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enable_irq();
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IO::out8(0x1F6, 0xA0); // 0xB0 for 2nd device
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IO::out8(0x3F6, 0xA0); // 0xB0 for 2nd device
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IO::out8(IDE0_COMMAND, IDENTIFY_DRIVE);
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enable_irq();
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wait_for_irq();
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ByteBuffer wbuf = ByteBuffer::create_uninitialized(512);
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ByteBuffer bbuf = ByteBuffer::create_uninitialized(512);
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byte* b = bbuf.pointer();
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word* w = (word*)wbuf.pointer();
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const word* wbufbase = (word*)wbuf.pointer();
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for (dword i = 0; i < 256; ++i) {
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word data = IO::in16(IDE0_DATA);
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*(w++) = data;
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*(b++) = MSB(data);
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*(b++) = LSB(data);
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}
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// "Unpad" the device name string.
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for (dword i = 93; i > 54 && bbuf[i] == ' '; --i)
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bbuf[i] = 0;
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m_cylinders = wbufbase[1];
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m_heads = wbufbase[3];
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m_sectors_per_track = wbufbase[6];
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kprintf(
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"IDEDiskDevice: Master=\"%s\", C/H/Spt=%u/%u/%u\n",
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bbuf.pointer() + 54,
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m_cylinders,
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m_heads,
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m_sectors_per_track
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);
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// Let's try to set up DMA transfers.
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if (!m_pci_address.is_null()) {
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m_prdt.end_of_table = 0x8000;
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PCI::enable_bus_mastering(m_pci_address);
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m_bus_master_base = PCI::get_BAR4(m_pci_address) & 0xfffc;
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dbgprintf("PIIX Bus master IDE: I/O @ %x\n", m_bus_master_base);
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}
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}
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static void wait_400ns(word io_base)
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{
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for (int i = 0; i < 4; ++i)
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IO::in8(io_base + ATA_REG_ALTSTATUS);
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}
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bool IDEDiskDevice::read_sector_with_dma(dword lba, byte* outbuf)
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{
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LOCKER(m_lock);
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#ifdef DISK_DEBUG
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dbgprintf("%s(%u): IDEDiskDevice::read_sector_with_dma (%u) -> %p\n",
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current->process().name().characters(),
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current->pid(), lba, outbuf);
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#endif
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disable_irq();
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m_prdt.offset = PhysicalAddress((dword)outbuf);
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m_prdt.size = 512;
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// Stop bus master
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IO::out8(m_bus_master_base, 0);
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// Write the PRDT location
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IO::out32(m_bus_master_base + 4, (dword)&m_prdt);
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// Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
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IO::out8(m_bus_master_base + 2, IO::in8(m_bus_master_base + 2) | 0x6);
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// Set transfer direction
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IO::out8(m_bus_master_base, 0x8);
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m_interrupted = false;
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enable_irq();
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while (IO::in8(IDE0_STATUS) & BUSY);
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word io_base = 0x1f0;
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bool is_slave = false;
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IO::out8(io_base + ATA_REG_CONTROL, 0);
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IO::out8(io_base + ATA_REG_HDDEVSEL, 0xe0 | (is_slave << 4));
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wait_400ns(io_base);
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IO::out8(io_base + ATA_REG_FEATURES, 0);
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IO::out8(io_base + ATA_REG_SECCOUNT0, 0);
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IO::out8(io_base + ATA_REG_LBA0, 0);
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IO::out8(io_base + ATA_REG_LBA1, 0);
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IO::out8(io_base + ATA_REG_LBA2, 0);
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IO::out8(io_base + ATA_REG_SECCOUNT0, 1);
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IO::out8(io_base + ATA_REG_LBA0, (lba & 0x000000ff) >> 0);
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IO::out8(io_base + ATA_REG_LBA1, (lba & 0x0000ff00) >> 8);
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IO::out8(io_base + ATA_REG_LBA2, (lba & 0x00ff0000) >> 16);
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for (;;) {
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auto status = IO::in8(io_base + ATA_REG_STATUS);
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if (!(status & ATA_SR_BSY) && (status & ATA_SR_DRDY))
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break;
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}
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IO::out8(io_base + ATA_REG_COMMAND, ATA_CMD_READ_DMA_EXT);
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wait_400ns(io_base);
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// Start bus master
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IO::out8(m_bus_master_base, 0x9);
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wait_for_irq();
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disable_irq();
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if (m_device_error)
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return false;
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// I read somewhere that this may trigger a cache flush so let's do it.
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IO::out8(m_bus_master_base + 2, IO::in8(m_bus_master_base + 2) | 0x6);
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return true;
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}
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bool IDEDiskDevice::read_sectors(dword start_sector, word count, byte* outbuf)
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{
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ASSERT(count <= 256);
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LOCKER(m_lock);
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#ifdef DISK_DEBUG
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dbgprintf("%s: Disk::read_sectors request (%u sector(s) @ %u)\n",
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current->process().name().characters(),
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count,
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start_sector);
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#endif
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disable_irq();
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while (IO::in8(IDE0_STATUS) & BUSY);
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#ifdef DISK_DEBUG
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kprintf("IDEDiskDevice: Reading %u sector(s) @ LBA %u\n", count, start_sector);
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#endif
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IO::out8(0x1f2, count == 256 ? 0 : LSB(count));
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IO::out8(0x1f3, start_sector & 0xff);
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IO::out8(0x1f4, (start_sector >> 8) & 0xff);
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IO::out8(0x1f5, (start_sector >> 16) & 0xff);
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IO::out8(0x1f6, 0xe0 | ((start_sector >> 24) & 0xf)); // 0xf0 for 2nd device
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IO::out8(0x3F6, 0x08);
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while (!(IO::in8(IDE0_STATUS) & DRDY));
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IO::out8(IDE0_COMMAND, READ_SECTORS);
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m_interrupted = false;
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enable_irq();
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wait_for_irq();
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if (m_device_error)
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return false;
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byte status = IO::in8(0x1f7);
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ASSERT(status & DRQ);
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#ifdef DISK_DEBUG
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kprintf("Retrieving %u bytes (status=%b), outbuf=%p...\n", count * 512, status, outbuf);
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#endif
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IO::repeated_in16(IDE0_DATA, outbuf, count * 256);
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return true;
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}
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bool IDEDiskDevice::write_sectors(dword start_sector, word count, const byte* data)
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{
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ASSERT(count <= 256);
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LOCKER(m_lock);
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#ifdef DISK_DEBUG
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dbgprintf("%s(%u): IDEDiskDevice::write_sectors request (%u sector(s) @ %u)\n",
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current->process().name().characters(),
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current->pid(),
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count,
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start_sector);
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#endif
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disable_irq();
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while (IO::in8(IDE0_STATUS) & BUSY);
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//dbgprintf("IDEDiskDevice: Writing %u sector(s) @ LBA %u\n", count, start_sector);
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IO::out8(0x1f2, count == 256 ? 0 : LSB(count));
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IO::out8(0x1f3, start_sector & 0xff);
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IO::out8(0x1f4, (start_sector >> 8) & 0xff);
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IO::out8(0x1f5, (start_sector >> 16) & 0xff);
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IO::out8(0x1f6, 0xe0 | ((start_sector >> 24) & 0xf)); // 0xf0 for 2nd device
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IO::out8(0x3F6, 0x08);
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IO::out8(IDE0_COMMAND, WRITE_SECTORS);
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while (!(IO::in8(IDE0_STATUS) & DRQ));
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byte status = IO::in8(0x1f7);
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ASSERT(status & DRQ);
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IO::repeated_out16(IDE0_DATA, data, count * 256);
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m_interrupted = false;
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enable_irq();
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wait_for_irq();
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disable_irq();
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IO::out8(IDE0_COMMAND, FLUSH_CACHE);
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while (IO::in8(IDE0_STATUS) & BUSY);
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m_interrupted = false;
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enable_irq();
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wait_for_irq();
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return !m_device_error;
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}
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