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https://github.com/RGBCube/serenity
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1f9d3a3523
There are now 2 separate classes for almost the same object type: - EnumerableDeviceIdentifier, which is used in the enumeration code for all PCI host controller classes. This is allowed to be moved and copied, as it doesn't support ref-counting. - DeviceIdentifier, which inherits from EnumerableDeviceIdentifier. This class uses ref-counting, and is not allowed to be copied. It has a spinlock member in its structure to allow safely executing complicated IO sequences on a PCI device and its space configuration. There's a static method that allows a quick conversion from EnumerableDeviceIdentifier to DeviceIdentifier while creating a NonnullRefPtr out of it. The reason for doing this is for the sake of integrity and reliablity of the system in 2 places: - Ensure that "complicated" tasks that rely on manipulating PCI device registers are done in a safe manner. For example, determining a PCI BAR space size requires multiple read and writes to the same register, and if another CPU tries to do something else with our selected register, then the result will be a catastrophe. - Allow the PCI API to have a united form around a shared object which actually holds much more data than the PCI::Address structure. This is fundamental if we want to do certain types of optimizations, and be able to support more features of the PCI bus in the foreseeable future. This patch already has several implications: - All PCI::Device(s) hold a reference to a DeviceIdentifier structure being given originally from the PCI::Access singleton. This means that all instances of DeviceIdentifier structures are located in one place, and all references are pointing to that location. This ensures that locking the operation spinlock will take effect in all the appropriate places. - We no longer support adding PCI host controllers and then immediately allow for enumerating it with a lambda function. It was found that this method is extremely broken and too much complicated to work reliably with the new paradigm being introduced in this patch. This means that for Volume Management Devices (Intel VMD devices), we simply first enumerate the PCI bus for such devices in the storage code, and if we find a device, we attach it in the PCI::Access method which will scan for devices behind that bridge and will add new DeviceIdentifier(s) objects to its internal Vector. Afterwards, we just continue as usual with scanning for actual storage controllers, so we will find a corresponding NVMe controllers if there were any behind that VMD bridge.
83 lines
2.6 KiB
C++
83 lines
2.6 KiB
C++
/*
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* Copyright (c) 2021, Pankaj R <pankydev8@gmail.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/OwnPtr.h>
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#include <AK/Time.h>
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#include <AK/Tuple.h>
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#include <AK/Types.h>
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#include <Kernel/Bus/PCI/Device.h>
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#include <Kernel/Library/LockRefPtr.h>
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#include <Kernel/Library/NonnullLockRefPtr.h>
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#include <Kernel/Library/NonnullLockRefPtrVector.h>
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#include <Kernel/Locking/Spinlock.h>
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#include <Kernel/Memory/TypedMapping.h>
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#include <Kernel/Storage/NVMe/NVMeDefinitions.h>
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#include <Kernel/Storage/NVMe/NVMeNameSpace.h>
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#include <Kernel/Storage/NVMe/NVMeQueue.h>
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#include <Kernel/Storage/StorageController.h>
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namespace Kernel {
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class NVMeController : public PCI::Device
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, public StorageController {
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public:
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static ErrorOr<NonnullLockRefPtr<NVMeController>> try_initialize(PCI::DeviceIdentifier const&, bool is_queue_polled);
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ErrorOr<void> initialize(bool is_queue_polled);
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LockRefPtr<StorageDevice> device(u32 index) const override;
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size_t devices_count() const override;
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virtual StringView device_name() const override { return "NVMeController"sv; }
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protected:
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bool reset() override;
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bool shutdown() override;
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void complete_current_request(AsyncDeviceRequest::RequestResult result) override;
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public:
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bool reset_controller();
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bool start_controller();
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u32 get_admin_q_dept();
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u16 submit_admin_command(NVMeSubmission& sub, bool sync = false)
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{
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// First queue is always the admin queue
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if (sync) {
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return m_admin_queue->submit_sync_sqe(sub);
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}
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m_admin_queue->submit_sqe(sub);
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return 0;
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}
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bool is_admin_queue_ready() { return m_admin_queue_ready; };
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void set_admin_queue_ready_flag() { m_admin_queue_ready = true; };
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private:
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NVMeController(PCI::DeviceIdentifier const&, u32 hardware_relative_controller_id);
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ErrorOr<void> identify_and_init_namespaces();
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Tuple<u64, u8> get_ns_features(IdentifyNamespace& identify_data_struct);
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ErrorOr<void> create_admin_queue(Optional<u8> irq);
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ErrorOr<void> create_io_queue(u8 qid, Optional<u8> irq);
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void calculate_doorbell_stride()
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{
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m_dbl_stride = (m_controller_regs->cap >> CAP_DBL_SHIFT) & CAP_DBL_MASK;
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}
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bool wait_for_ready(bool);
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private:
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LockRefPtr<NVMeQueue> m_admin_queue;
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NonnullLockRefPtrVector<NVMeQueue> m_queues;
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NonnullLockRefPtrVector<NVMeNameSpace> m_namespaces;
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Memory::TypedMapping<ControllerRegister volatile> m_controller_regs;
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bool m_admin_queue_ready { false };
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size_t m_device_count { 0 };
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AK::Time m_ready_timeout;
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u32 m_bar { 0 };
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u8 m_dbl_stride { 0 };
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static Atomic<u8> s_controller_id;
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};
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}
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