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https://github.com/RGBCube/serenity
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f96e8e97e6
IDEChannel which is an ATAPort derived class holded a NonnullRefPtr to a parent IDEController, although we can easily defer the usage of it to not be in the IDEChannel code at all, so it allows to keep NonnullRefPtr to the parent ATAController in the ATAPort base class and only there.
331 lines
12 KiB
C++
331 lines
12 KiB
C++
/*
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* Copyright (c) 2018-2021, Andreas Kling <kling@serenityos.org>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <AK/ByteBuffer.h>
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#include <AK/Singleton.h>
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#include <AK/StringView.h>
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#include <Kernel/Arch/x86/IO.h>
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#include <Kernel/Bus/PCI/API.h>
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#include <Kernel/Memory/MemoryManager.h>
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#include <Kernel/Process.h>
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#include <Kernel/Sections.h>
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#include <Kernel/Storage/ATA/ATADiskDevice.h>
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#include <Kernel/Storage/ATA/Definitions.h>
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#include <Kernel/Storage/ATA/GenericIDE/Channel.h>
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#include <Kernel/Storage/ATA/GenericIDE/Controller.h>
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#include <Kernel/WorkQueue.h>
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namespace Kernel {
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#define PATA_PRIMARY_IRQ 14
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#define PATA_SECONDARY_IRQ 15
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UNMAP_AFTER_INIT NonnullRefPtr<IDEChannel> IDEChannel::create(IDEController const& controller, IOAddressGroup io_group, ChannelType type)
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{
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auto ata_identify_data_buffer = KBuffer::try_create_with_size("ATA Identify Page"sv, 4096, Memory::Region::Access::ReadWrite, AllocationStrategy::AllocateNow).release_value();
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return adopt_ref(*new IDEChannel(controller, io_group, type, move(ata_identify_data_buffer)));
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}
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UNMAP_AFTER_INIT NonnullRefPtr<IDEChannel> IDEChannel::create(IDEController const& controller, u8 irq, IOAddressGroup io_group, ChannelType type)
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{
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auto ata_identify_data_buffer = KBuffer::try_create_with_size("ATA Identify Page"sv, 4096, Memory::Region::Access::ReadWrite, AllocationStrategy::AllocateNow).release_value();
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return adopt_ref(*new IDEChannel(controller, irq, io_group, type, move(ata_identify_data_buffer)));
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}
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StringView IDEChannel::channel_type_string() const
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{
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if (m_channel_type == ChannelType::Primary)
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return "Primary"sv;
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return "Secondary"sv;
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}
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bool IDEChannel::select_device_and_wait_until_not_busy(DeviceType device_type, size_t milliseconds_timeout)
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{
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IO::delay(20);
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u8 slave = device_type == DeviceType::Slave;
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m_io_group.io_base().offset(ATA_REG_HDDEVSEL).out<u8>(0xA0 | (slave << 4)); // First, we need to select the drive itself
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IO::delay(20);
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size_t time_elapsed = 0;
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while (m_io_group.control_base().in<u8>() & ATA_SR_BSY && time_elapsed <= milliseconds_timeout) {
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IO::delay(1000);
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time_elapsed++;
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}
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return time_elapsed <= milliseconds_timeout;
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}
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ErrorOr<void> IDEChannel::port_phy_reset()
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{
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MutexLocker locker(m_lock);
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SpinlockLocker hard_locker(m_hard_lock);
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// reset the channel
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u8 device_control = m_io_group.control_base().in<u8>();
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// Wait 30 milliseconds
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IO::delay(30000);
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m_io_group.control_base().out<u8>(device_control | (1 << 2));
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// Wait 30 milliseconds
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IO::delay(30000);
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m_io_group.control_base().out<u8>(device_control);
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// Wait up to 30 seconds before failing
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if (!select_device_and_wait_until_not_busy(DeviceType::Master, 30000)) {
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dbgln("IDEChannel: reset failed, busy flag on master stuck");
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return Error::from_errno(EBUSY);
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}
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// Wait up to 30 seconds before failing
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if (!select_device_and_wait_until_not_busy(DeviceType::Slave, 30000)) {
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dbgln("IDEChannel: reset failed, busy flag on slave stuck");
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return Error::from_errno(EBUSY);
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}
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return {};
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}
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ErrorOr<void> IDEChannel::allocate_resources_for_pci_ide_controller(Badge<PCIIDEController>, bool force_pio)
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{
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return allocate_resources(force_pio);
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}
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ErrorOr<void> IDEChannel::allocate_resources_for_isa_ide_controller(Badge<ISAIDEController>)
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{
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return allocate_resources(false);
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}
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UNMAP_AFTER_INIT ErrorOr<void> IDEChannel::allocate_resources(bool force_pio)
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{
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dbgln_if(PATA_DEBUG, "IDEChannel: {} IO base: {}", channel_type_string(), m_io_group.io_base());
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dbgln_if(PATA_DEBUG, "IDEChannel: {} control base: {}", channel_type_string(), m_io_group.control_base());
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if (m_io_group.bus_master_base().has_value())
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dbgln_if(PATA_DEBUG, "IDEChannel: {} bus master base: {}", channel_type_string(), m_io_group.bus_master_base().value());
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else
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dbgln_if(PATA_DEBUG, "IDEChannel: {} bus master base disabled", channel_type_string());
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if (!force_pio) {
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m_dma_enabled = true;
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VERIFY(m_io_group.bus_master_base().has_value());
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// Let's try to set up DMA transfers.
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m_prdt_region = TRY(MM.allocate_dma_buffer_page("IDE PRDT"sv, Memory::Region::Access::ReadWrite, m_prdt_page));
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VERIFY(!m_prdt_page.is_null());
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m_dma_buffer_region = TRY(MM.allocate_dma_buffer_page("IDE DMA region"sv, Memory::Region::Access::ReadWrite, m_dma_buffer_page));
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VERIFY(!m_dma_buffer_page.is_null());
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prdt().end_of_table = 0x8000;
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// clear bus master interrupt status
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m_io_group.bus_master_base().value().offset(2).out<u8>(m_io_group.bus_master_base().value().offset(2).in<u8>() | 4);
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}
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return {};
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}
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UNMAP_AFTER_INIT IDEChannel::IDEChannel(IDEController const& controller, u8 irq, IOAddressGroup io_group, ChannelType type, NonnullOwnPtr<KBuffer> ata_identify_data_buffer)
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: ATAPort(controller, (type == ChannelType::Primary ? 0 : 1), move(ata_identify_data_buffer))
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, IRQHandler(irq)
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, m_channel_type(type)
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, m_io_group(io_group)
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{
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}
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UNMAP_AFTER_INIT IDEChannel::IDEChannel(IDEController const& controller, IOAddressGroup io_group, ChannelType type, NonnullOwnPtr<KBuffer> ata_identify_data_buffer)
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: ATAPort(controller, (type == ChannelType::Primary ? 0 : 1), move(ata_identify_data_buffer))
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, IRQHandler(type == ChannelType::Primary ? PATA_PRIMARY_IRQ : PATA_SECONDARY_IRQ)
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, m_channel_type(type)
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, m_io_group(io_group)
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{
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}
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UNMAP_AFTER_INIT IDEChannel::~IDEChannel() = default;
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bool IDEChannel::handle_irq(RegisterState const&)
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{
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auto result = handle_interrupt_after_dma_transaction();
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// FIXME: Propagate errors properly
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VERIFY(!result.is_error());
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return result.release_value();
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}
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ErrorOr<void> IDEChannel::stop_busmastering()
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{
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VERIFY(m_lock.is_locked());
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VERIFY(m_io_group.bus_master_base().has_value());
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m_io_group.bus_master_base().value().out<u8>(0);
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return {};
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}
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ErrorOr<void> IDEChannel::start_busmastering(TransactionDirection direction)
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{
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VERIFY(m_lock.is_locked());
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VERIFY(m_io_group.bus_master_base().has_value());
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m_io_group.bus_master_base().value().out<u8>(direction != TransactionDirection::Write ? 0x9 : 0x1);
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return {};
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}
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ErrorOr<void> IDEChannel::force_busmastering_status_clean()
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{
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VERIFY(m_lock.is_locked());
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VERIFY(m_io_group.bus_master_base().has_value());
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m_io_group.bus_master_base().value().offset(2).out<u8>(m_io_group.bus_master_base().value().offset(2).in<u8>() | 4);
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return {};
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}
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ErrorOr<u8> IDEChannel::busmastering_status()
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{
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VERIFY(m_io_group.bus_master_base().has_value());
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return m_io_group.bus_master_base().value().offset(2).in<u8>();
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}
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ErrorOr<void> IDEChannel::prepare_transaction_with_busmastering(TransactionDirection direction, PhysicalAddress prdt_buffer)
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{
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VERIFY(m_lock.is_locked());
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m_io_group.bus_master_base().value().offset(4).out<u32>(prdt_buffer.get());
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m_io_group.bus_master_base().value().out<u8>(direction != TransactionDirection::Write ? 0x8 : 0);
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// Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
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m_io_group.bus_master_base().value().offset(2).out<u8>(m_io_group.bus_master_base().value().offset(2).in<u8>() | 0x6);
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return {};
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}
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ErrorOr<void> IDEChannel::initiate_transaction(TransactionDirection)
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{
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VERIFY(m_lock.is_locked());
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return {};
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}
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ErrorOr<u8> IDEChannel::task_file_status()
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{
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VERIFY(m_lock.is_locked());
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return m_io_group.control_base().in<u8>();
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}
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ErrorOr<u8> IDEChannel::task_file_error()
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{
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VERIFY(m_lock.is_locked());
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return m_io_group.io_base().offset(ATA_REG_ERROR).in<u8>();
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}
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ErrorOr<bool> IDEChannel::detect_presence_on_selected_device()
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{
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VERIFY(m_lock.is_locked());
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m_io_group.io_base().offset(ATA_REG_SECCOUNT0).out<u8>(0x55);
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m_io_group.io_base().offset(ATA_REG_LBA0).out<u8>(0xAA);
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m_io_group.io_base().offset(ATA_REG_SECCOUNT0).out<u8>(0xAA);
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m_io_group.io_base().offset(ATA_REG_LBA0).out<u8>(0x55);
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m_io_group.io_base().offset(ATA_REG_SECCOUNT0).out<u8>(0x55);
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m_io_group.io_base().offset(ATA_REG_LBA0).out<u8>(0xAA);
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auto nsectors_value = m_io_group.io_base().offset(ATA_REG_SECCOUNT0).in<u8>();
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auto lba0 = m_io_group.io_base().offset(ATA_REG_LBA0).in<u8>();
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if (lba0 == 0xAA && nsectors_value == 0x55)
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return true;
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return false;
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}
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ErrorOr<void> IDEChannel::wait_if_busy_until_timeout(size_t timeout_in_milliseconds)
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{
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size_t time_elapsed = 0;
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while (m_io_group.control_base().in<u8>() & ATA_SR_BSY && time_elapsed <= timeout_in_milliseconds) {
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IO::delay(1000);
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time_elapsed++;
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}
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if (time_elapsed <= timeout_in_milliseconds)
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return {};
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return Error::from_errno(EBUSY);
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}
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ErrorOr<void> IDEChannel::force_clear_interrupts()
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{
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VERIFY(m_lock.is_locked());
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m_io_group.io_base().offset(ATA_REG_STATUS).in<u8>();
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return {};
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}
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ErrorOr<void> IDEChannel::load_taskfile_into_registers(ATAPort::TaskFile const& task_file, LBAMode lba_mode, size_t completion_timeout_in_milliseconds)
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{
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VERIFY(m_lock.is_locked());
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VERIFY(m_hard_lock.is_locked());
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u8 head = 0;
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if (lba_mode == LBAMode::FortyEightBit) {
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head = 0;
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} else if (lba_mode == LBAMode::TwentyEightBit) {
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head = (task_file.lba_high[0] & 0x0F);
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}
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// Note: Preserve the selected drive, always use LBA addressing
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auto driver_register = ((m_io_group.io_base().offset(ATA_REG_HDDEVSEL).in<u8>() & (1 << 4)) | (head | (1 << 5) | (1 << 6)));
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m_io_group.io_base().offset(ATA_REG_HDDEVSEL).out<u8>(driver_register);
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IO::delay(50);
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if (lba_mode == LBAMode::FortyEightBit) {
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m_io_group.io_base().offset(ATA_REG_SECCOUNT1).out<u8>((task_file.count >> 8) & 0xFF);
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m_io_group.io_base().offset(ATA_REG_LBA3).out<u8>(task_file.lba_high[0]);
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m_io_group.io_base().offset(ATA_REG_LBA4).out<u8>(task_file.lba_high[1]);
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m_io_group.io_base().offset(ATA_REG_LBA5).out<u8>(task_file.lba_high[2]);
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}
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m_io_group.io_base().offset(ATA_REG_SECCOUNT0).out<u8>(task_file.count & 0xFF);
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m_io_group.io_base().offset(ATA_REG_LBA0).out<u8>(task_file.lba_low[0]);
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m_io_group.io_base().offset(ATA_REG_LBA1).out<u8>(task_file.lba_low[1]);
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m_io_group.io_base().offset(ATA_REG_LBA2).out<u8>(task_file.lba_low[2]);
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// FIXME: Set a timeout here?
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size_t time_elapsed = 0;
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for (;;) {
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if (time_elapsed > completion_timeout_in_milliseconds)
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return Error::from_errno(EBUSY);
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// FIXME: Use task_file_status method
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auto status = m_io_group.control_base().in<u8>();
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if (!(status & ATA_SR_BSY) && (status & ATA_SR_DRDY))
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break;
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IO::delay(1000);
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time_elapsed++;
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}
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m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(task_file.command);
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return {};
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}
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ErrorOr<void> IDEChannel::device_select(size_t device_index)
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{
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VERIFY(m_lock.is_locked());
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if (device_index > 1)
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return Error::from_errno(EINVAL);
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IO::delay(20);
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m_io_group.io_base().offset(ATA_REG_HDDEVSEL).out<u8>(0xA0 | ((device_index) << 4));
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IO::delay(20);
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return {};
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}
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ErrorOr<void> IDEChannel::enable_interrupts()
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{
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VERIFY(m_lock.is_locked());
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m_io_group.control_base().out<u8>(0);
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m_interrupts_enabled = true;
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return {};
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}
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ErrorOr<void> IDEChannel::disable_interrupts()
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{
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VERIFY(m_lock.is_locked());
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m_io_group.control_base().out<u8>(1 << 1);
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m_interrupts_enabled = false;
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return {};
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}
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ErrorOr<void> IDEChannel::read_pio_data_to_buffer(UserOrKernelBuffer& buffer, size_t block_offset, size_t words_count)
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{
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VERIFY(m_lock.is_locked());
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VERIFY(words_count == 256);
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for (u32 i = 0; i < 256; ++i) {
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u16 data = m_io_group.io_base().offset(ATA_REG_DATA).in<u16>();
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// FIXME: Don't assume 512 bytes sector
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TRY(buffer.write(&data, block_offset * 512 + (i * 2), 2));
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}
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return {};
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}
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ErrorOr<void> IDEChannel::write_pio_data_from_buffer(UserOrKernelBuffer const& buffer, size_t block_offset, size_t words_count)
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{
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VERIFY(m_lock.is_locked());
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VERIFY(words_count == 256);
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for (u32 i = 0; i < 256; ++i) {
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u16 buf;
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// FIXME: Don't assume 512 bytes sector
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TRY(buffer.read(&buf, block_offset * 512 + (i * 2), 2));
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IO::out16(m_io_group.io_base().offset(ATA_REG_DATA).get(), buf);
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}
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return {};
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}
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}
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