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We can now test a _very_ basic transaction via `do_debug_transfer()`. This function merely attaches some TDs to the LSCTRL queue head and points some input and output buffers. We then sense an interrupt with USBSTS value of 1, meaning Interrupt On Completion (of the transaction). At this point, the input buffer is filled with some data.
102 lines
3.8 KiB
C++
102 lines
3.8 KiB
C++
/*
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* Copyright (c) 2020, Andreas Kling <kling@serenityos.org>
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* Copyright (c) 2020-2021, Jesse Buhagiar <jooster669@gmail.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#pragma once
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#include <AK/NonnullOwnPtr.h>
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#include <Kernel/Devices/USB/UHCIDescriptorTypes.h>
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#include <Kernel/IO.h>
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#include <Kernel/PCI/Device.h>
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#include <Kernel/Process.h>
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#include <Kernel/Time/TimeManagement.h>
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#include <Kernel/VM/ContiguousVMObject.h>
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namespace Kernel::USB {
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class UHCIController final : public PCI::Device {
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public:
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static void detect();
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static UHCIController& the();
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virtual ~UHCIController() override;
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void reset();
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void stop();
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void start();
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void spawn_port_proc();
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void do_debug_transfer();
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private:
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UHCIController(PCI::Address, PCI::ID);
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u16 read_usbcmd() { return m_io_base.offset(0).in<u16>(); }
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u16 read_usbsts() { return m_io_base.offset(0x2).in<u16>(); }
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u16 read_usbintr() { return m_io_base.offset(0x4).in<u16>(); }
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u16 read_frnum() { return m_io_base.offset(0x6).in<u16>(); }
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u32 read_flbaseadd() { return m_io_base.offset(0x8).in<u32>(); }
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u8 read_sofmod() { return m_io_base.offset(0xc).in<u8>(); }
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u16 read_portsc1() { return m_io_base.offset(0x10).in<u16>(); }
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u16 read_portsc2() { return m_io_base.offset(0x12).in<u16>(); }
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void write_usbcmd(u16 value) { m_io_base.offset(0).out(value); }
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void write_usbsts(u16 value) { m_io_base.offset(0x2).out(value); }
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void write_usbintr(u16 value) { m_io_base.offset(0x4).out(value); }
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void write_frnum(u16 value) { m_io_base.offset(0x6).out(value); }
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void write_flbaseadd(u32 value) { m_io_base.offset(0x8).out(value); }
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void write_sofmod(u8 value) { m_io_base.offset(0xc).out(value); }
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void write_portsc1(u16 value) { m_io_base.offset(0x10).out(value); }
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void write_portsc2(u16 value) { m_io_base.offset(0x12).out(value); }
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virtual void handle_irq(const RegisterState&) override;
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void create_structures();
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void setup_schedule();
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QueueHead* allocate_queue_head() const;
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TransferDescriptor* allocate_transfer_descriptor() const;
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private:
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IOAddress m_io_base;
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Vector<QueueHead*> m_free_qh_pool;
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Vector<TransferDescriptor*> m_free_td_pool;
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Vector<TransferDescriptor*> m_iso_td_list;
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QueueHead* m_interrupt_transfer_queue;
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QueueHead* m_lowspeed_control_qh;
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QueueHead* m_fullspeed_control_qh;
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QueueHead* m_bulk_qh;
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QueueHead* m_dummy_qh; // Needed for PIIX4 hack
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OwnPtr<Region> m_framelist;
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OwnPtr<Region> m_qh_pool;
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OwnPtr<Region> m_td_pool;
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OwnPtr<Region> m_td_buffer_region;
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};
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}
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