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https://github.com/RGBCube/serenity
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Kernel: Rename Aarch64Registers -> Registers and add Aarch64 namespace
This commit is contained in:
James Mintram
Brian Gianforcaro
parent
271b9b8da3
commit
34709c8d39
4 changed files with 71 additions and 70 deletions
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@ -6,7 +6,7 @@
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#pragma once
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#include <Kernel/Arch/aarch64/Aarch64Registers.h>
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#include <Kernel/Arch/aarch64/Registers.h>
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namespace Kernel {
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@ -9,11 +9,11 @@
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#include <AK/Types.h>
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namespace Kernel {
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namespace Kernel::Aarch64 {
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// https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/ID-AA64MMFR0-EL1--AArch64-Memory-Model-Feature-Register-0
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// Memory Model Feature Register 0
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struct Aarch64_ID_AA64MMFR0_EL1 {
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struct ID_AA64MMFR0_EL1 {
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int PARange : 4;
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int ASIDBits : 4;
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int BigEnd : 4;
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@ -30,9 +30,9 @@ struct Aarch64_ID_AA64MMFR0_EL1 {
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int FGT : 4;
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int ECV : 4;
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static inline Aarch64_ID_AA64MMFR0_EL1 read()
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static inline ID_AA64MMFR0_EL1 read()
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{
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Aarch64_ID_AA64MMFR0_EL1 feature_register;
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ID_AA64MMFR0_EL1 feature_register;
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asm("mrs %[value], ID_AA64MMFR0_EL1"
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: [value] "=r"(feature_register));
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@ -43,7 +43,7 @@ struct Aarch64_ID_AA64MMFR0_EL1 {
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// https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/TCR-EL1--Translation-Control-Register--EL1-
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// Translation Control Register
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struct Aarch64_TCR_EL1 {
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struct TCR_EL1 {
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enum Shareability {
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NonSharable = 0b00,
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@ -130,14 +130,14 @@ struct Aarch64_TCR_EL1 {
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int DS : 1;
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int RES0_2 : 4;
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static inline void write(Aarch64_TCR_EL1 tcr_el1)
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static inline void write(TCR_EL1 tcr_el1)
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{
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asm("msr tcr_el1, %[value]" ::[value] "r"(tcr_el1));
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}
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static inline Aarch64_TCR_EL1 read()
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static inline TCR_EL1 read()
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{
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Aarch64_TCR_EL1 tcr_el1;
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TCR_EL1 tcr_el1;
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asm("mrs %[value], tcr_el1_el1"
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: [value] "=r"(tcr_el1));
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@ -145,16 +145,16 @@ struct Aarch64_TCR_EL1 {
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return tcr_el1;
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}
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static inline constexpr Aarch64_TCR_EL1 reset_value()
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static inline constexpr TCR_EL1 reset_value()
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{
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return {};
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}
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};
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static_assert(sizeof(Aarch64_TCR_EL1) == 8);
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static_assert(sizeof(TCR_EL1) == 8);
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// https://developer.arm.com/documentation/ddi0595/2021-03/AArch64-Registers/SCTLR-EL1--System-Control-Register--EL1-
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// System Control Register
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struct Aarch64_SCTLR_EL1 {
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struct SCTLR_EL1 {
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int M : 1;
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int A : 1;
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int C : 1;
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@ -205,14 +205,14 @@ struct Aarch64_SCTLR_EL1 {
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int EPAN : 1;
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int _reserved58 : 6 = 0;
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static inline void write(Aarch64_SCTLR_EL1 sctlr_el1)
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static inline void write(SCTLR_EL1 sctlr_el1)
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{
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asm("msr sctlr_el1, %[value]" ::[value] "r"(sctlr_el1));
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}
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static inline Aarch64_SCTLR_EL1 read()
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static inline SCTLR_EL1 read()
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{
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Aarch64_SCTLR_EL1 sctlr;
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SCTLR_EL1 sctlr;
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asm("mrs %[value], sctlr_el1"
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: [value] "=r"(sctlr));
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@ -220,9 +220,9 @@ struct Aarch64_SCTLR_EL1 {
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return sctlr;
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}
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static inline constexpr Aarch64_SCTLR_EL1 reset_value()
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static inline constexpr SCTLR_EL1 reset_value()
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{
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Aarch64_SCTLR_EL1 system_control_register_el1 = {};
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SCTLR_EL1 system_control_register_el1 = {};
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system_control_register_el1.LSMAOE = 1;
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system_control_register_el1.nTLSMD = 1;
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system_control_register_el1.SPAN = 1;
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@ -230,11 +230,11 @@ struct Aarch64_SCTLR_EL1 {
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return system_control_register_el1;
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}
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};
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static_assert(sizeof(Aarch64_SCTLR_EL1) == 8);
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static_assert(sizeof(SCTLR_EL1) == 8);
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// https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/HCR-EL2--Hypervisor-Configuration-Register
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// Hypervisor Configuration Register
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struct Aarch64_HCR_EL2 {
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struct HCR_EL2 {
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int VM : 1;
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int SWIO : 1;
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int PTW : 1;
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@ -280,14 +280,14 @@ struct Aarch64_HCR_EL2 {
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int AT : 1 = 0;
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int _reserved45 : 18 = 0;
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static inline void write(Aarch64_HCR_EL2 hcr_el2)
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static inline void write(HCR_EL2 hcr_el2)
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{
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asm("msr hcr_el2, %[value]" ::[value] "r"(hcr_el2));
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}
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static inline Aarch64_HCR_EL2 read()
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static inline HCR_EL2 read()
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{
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Aarch64_HCR_EL2 spsr;
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HCR_EL2 spsr;
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asm("mrs %[value], hcr_el2"
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: [value] "=r"(spsr));
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@ -295,11 +295,11 @@ struct Aarch64_HCR_EL2 {
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return spsr;
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}
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};
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static_assert(sizeof(Aarch64_HCR_EL2) == 8);
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static_assert(sizeof(HCR_EL2) == 8);
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// https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/SCR-EL3--Secure-Configuration-Register
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// Secure Configuration Register
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struct Aarch64_SCR_EL3 {
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struct SCR_EL3 {
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int NS : 1;
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int IRQ : 1;
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int FIQ : 1;
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@ -336,14 +336,14 @@ struct Aarch64_SCR_EL3 {
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int HXEn : 1;
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int _reserved39 : 14 = 0;
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static inline void write(Aarch64_SCR_EL3 scr_el3)
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static inline void write(SCR_EL3 scr_el3)
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{
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asm("msr scr_el3, %[value]" ::[value] "r"(scr_el3));
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}
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static inline Aarch64_SCR_EL3 read()
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static inline SCR_EL3 read()
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{
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Aarch64_SCR_EL3 scr;
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SCR_EL3 scr;
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asm("mrs %[value], scr_el3"
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: [value] "=r"(scr));
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@ -351,9 +351,9 @@ struct Aarch64_SCR_EL3 {
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return scr;
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}
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};
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static_assert(sizeof(Aarch64_SCR_EL3) == 8);
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static_assert(sizeof(SCR_EL3) == 8);
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struct Aarch64_SPSR_EL2 {
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struct SPSR_EL2 {
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enum Mode : u16 {
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EL0t = 0b0000,
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EL1t = 0b0100,
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@ -385,14 +385,14 @@ struct Aarch64_SPSR_EL2 {
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int N : 1;
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int _reserved32 : 32 = 0;
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static inline void write(Aarch64_SPSR_EL2 spsr_el2)
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static inline void write(SPSR_EL2 spsr_el2)
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{
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asm("msr spsr_el2, %[value]" ::[value] "r"(spsr_el2));
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}
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static inline Aarch64_SPSR_EL2 read()
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static inline SPSR_EL2 read()
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{
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Aarch64_SPSR_EL2 spsr;
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SPSR_EL2 spsr;
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asm("mrs %[value], spsr_el2"
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: [value] "=r"(spsr));
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@ -400,11 +400,11 @@ struct Aarch64_SPSR_EL2 {
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return spsr;
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}
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};
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static_assert(sizeof(Aarch64_SPSR_EL2) == 8);
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static_assert(sizeof(SPSR_EL2) == 8);
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// https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/SPSR-EL3--Saved-Program-Status-Register--EL3-
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// Saved Program Status Register
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struct Aarch64_SPSR_EL3 {
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struct SPSR_EL3 {
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enum Mode : uint16_t {
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EL0t = 0b0000,
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EL1t = 0b0100,
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@ -434,14 +434,14 @@ struct Aarch64_SPSR_EL3 {
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int N : 1;
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int _reserved32 : 32 = 0;
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static inline void write(Aarch64_SPSR_EL3 spsr_el3)
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static inline void write(SPSR_EL3 spsr_el3)
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{
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asm("msr spsr_el3, %[value]" ::[value] "r"(spsr_el3));
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}
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static inline Aarch64_SPSR_EL3 read()
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static inline SPSR_EL3 read()
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{
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Aarch64_SPSR_EL3 spsr;
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SPSR_EL3 spsr;
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asm("mrs %[value], spsr_el3"
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: [value] "=r"(spsr));
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@ -449,18 +449,19 @@ struct Aarch64_SPSR_EL3 {
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return spsr;
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}
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};
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static_assert(sizeof(Aarch64_SPSR_EL3) == 8);
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static_assert(sizeof(SPSR_EL3) == 8);
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// https://developer.arm.com/documentation/ddi0595/2020-12/AArch64-Registers/MAIR-EL1--Memory-Attribute-Indirection-Register--EL1-?lang=en#fieldset_0-63_0
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// Memory Attribute Indirection Register
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struct Aarch64_MAIR_EL1 {
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struct MAIR_EL1 {
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using AttributeEncoding = uint8_t;
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AttributeEncoding Attr[8];
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static inline void write(Aarch64_MAIR_EL1 mair_el1)
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static inline void write(MAIR_EL1 mair_el1)
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{
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asm("msr mair_el1, %[value]" ::[value] "r"(mair_el1));
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}
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};
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static_assert(sizeof(Aarch64_MAIR_EL1) == 8);
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static_assert(sizeof(MAIR_EL1) == 8);
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}
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