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Kernel: Rename Aarch64Registers -> Registers and add Aarch64 namespace

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This commit is contained in:
James Mintram 2021-11-21 14:10:23 +00:00 • committed by Brian Gianforcaro
parent 271b9b8da3
commit 34709c8d39
4 changed files with 71 additions and 70 deletions
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26
Kernel/Prekernel/Arch/aarch64/PrekernelExceptions.cpp
View file

@ -5,7 +5,7 @@
*/
#include <Kernel/Arch/aarch64/Aarch64Asm.h>
#include <Kernel/Arch/aarch64/Aarch64Registers.h>
#include <Kernel/Arch/aarch64/Registers.h>
#include <Kernel/Prekernel/Arch/aarch64/Aarch64_asm_utils.h>
#include <Kernel/Prekernel/Arch/aarch64/Prekernel.h>
@ -18,16 +18,16 @@ namespace Prekernel {
static void drop_to_el2()
{
Aarch64_SCR_EL3 secure_configuration_register_el3 = {};
Aarch64::SCR_EL3 secure_configuration_register_el3 = {};
secure_configuration_register_el3.ST = 1; // Don't trap access to Counter-timer Physical Secure registers
secure_configuration_register_el3.RW = 1; // Lower level to use Aarch64
secure_configuration_register_el3.NS = 1; // Non-secure state
secure_configuration_register_el3.HCE = 1; // Enable Hypervisor instructions at all levels
Aarch64_SCR_EL3::write(secure_configuration_register_el3);
Aarch64::SCR_EL3::write(secure_configuration_register_el3);
Aarch64_SPSR_EL3 saved_program_status_register_el3 = {};
Aarch64::SPSR_EL3 saved_program_status_register_el3 = {};
// Mask (disable) all interrupts
saved_program_status_register_el3.A = 1;
@ -36,21 +36,21 @@ static void drop_to_el2()
saved_program_status_register_el3.D = 1;
// Indicate EL1 as exception origin mode (so we go back there)
saved_program_status_register_el3.M = Aarch64_SPSR_EL3::Mode::EL2t;
saved_program_status_register_el3.M = Aarch64::SPSR_EL3::Mode::EL2t;
// Set the register
Aarch64_SPSR_EL3::write(saved_program_status_register_el3);
Aarch64::SPSR_EL3::write(saved_program_status_register_el3);
// This will jump into os_start() below
enter_el2_from_el3();
}
static void drop_to_el1()
{
Aarch64_HCR_EL2 hypervisor_configuration_register_el2 = {};
Aarch64::HCR_EL2 hypervisor_configuration_register_el2 = {};
hypervisor_configuration_register_el2.RW = 1; // EL1 to use 64-bit mode
Aarch64_HCR_EL2::write(hypervisor_configuration_register_el2);
Aarch64::HCR_EL2::write(hypervisor_configuration_register_el2);
Aarch64_SPSR_EL2 saved_program_status_register_el2 = {};
Aarch64::SPSR_EL2 saved_program_status_register_el2 = {};
// Mask (disable) all interrupts
saved_program_status_register_el2.A = 1;
@ -58,15 +58,15 @@ static void drop_to_el1()
saved_program_status_register_el2.F = 1;
// Indicate EL1 as exception origin mode (so we go back there)
saved_program_status_register_el2.M = Aarch64_SPSR_EL2::Mode::EL1t;
saved_program_status_register_el2.M = Aarch64::SPSR_EL2::Mode::EL1t;
Aarch64_SPSR_EL2::write(saved_program_status_register_el2);
Aarch64::SPSR_EL2::write(saved_program_status_register_el2);
enter_el1_from_el2();
}
static void set_up_el1()
{
Aarch64_SCTLR_EL1 system_control_register_el1 = Aarch64_SCTLR_EL1::reset_value();
Aarch64::SCTLR_EL1 system_control_register_el1 = Aarch64::SCTLR_EL1::reset_value();
system_control_register_el1.UCT = 1; // Don't trap access to CTR_EL0
system_control_register_el1.nTWE = 1; // Don't trap WFE instructions
@ -77,7 +77,7 @@ static void set_up_el1()
system_control_register_el1.SA = 1; // Enable stack access alignment check for EL1
system_control_register_el1.A = 1; // Enable memory access alignment check
Aarch64_SCTLR_EL1::write(system_control_register_el1);
Aarch64::SCTLR_EL1::write(system_control_register_el1);
}
void drop_to_exception_level_1()

32
Kernel/Prekernel/Arch/aarch64/PrekernelMMU.cpp
View file

@ -9,7 +9,7 @@
#include <Kernel/Prekernel/Arch/aarch64/Prekernel.h>
#include <Kernel/Arch/aarch64/Aarch64Asm.h>
#include <Kernel/Arch/aarch64/Aarch64Registers.h>
#include <Kernel/Arch/aarch64/Registers.h>
#include <Kernel/Prekernel/Arch/aarch64/UART.h>
// Documentation here for Aarch64 Address Translations
@ -114,35 +114,35 @@ static void switch_to_page_table(u8* page_table)
static void activate_mmu()
{
Aarch64_MAIR_EL1 mair_el1 = {};
Aarch64::MAIR_EL1 mair_el1 = {};
mair_el1.Attr[0] = 0xFF; // Normal memory
mair_el1.Attr[1] = 0b00000100; // Device-nGnRE memory (non-cacheble)
Aarch64_MAIR_EL1::write(mair_el1);
Aarch64::MAIR_EL1::write(mair_el1);
// Configure cacheability attributes for memory associated with translation table walks
Aarch64_TCR_EL1 tcr_el1 = {};
Aarch64::TCR_EL1 tcr_el1 = {};
tcr_el1.SH1 = Aarch64_TCR_EL1::InnerShareable;
tcr_el1.ORGN1 = Aarch64_TCR_EL1::NormalMemory_Outer_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.IRGN1 = Aarch64_TCR_EL1::NormalMemory_Inner_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.SH1 = Aarch64::TCR_EL1::InnerShareable;
tcr_el1.ORGN1 = Aarch64::TCR_EL1::NormalMemory_Outer_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.IRGN1 = Aarch64::TCR_EL1::NormalMemory_Inner_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.SH0 = Aarch64_TCR_EL1::InnerShareable;
tcr_el1.ORGN0 = Aarch64_TCR_EL1::NormalMemory_Outer_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.IRGN0 = Aarch64_TCR_EL1::NormalMemory_Inner_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.SH0 = Aarch64::TCR_EL1::InnerShareable;
tcr_el1.ORGN0 = Aarch64::TCR_EL1::NormalMemory_Outer_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.IRGN0 = Aarch64::TCR_EL1::NormalMemory_Inner_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.TG1 = Aarch64_TCR_EL1::TG1GranuleSize::Size_4KB;
tcr_el1.TG0 = Aarch64_TCR_EL1::TG0GranuleSize::Size_4KB;
tcr_el1.TG1 = Aarch64::TCR_EL1::TG1GranuleSize::Size_4KB;
tcr_el1.TG0 = Aarch64::TCR_EL1::TG0GranuleSize::Size_4KB;
// Auto detect the Intermediate Physical Address Size
Aarch64_ID_AA64MMFR0_EL1 feature_register = Aarch64_ID_AA64MMFR0_EL1::read();
Aarch64::ID_AA64MMFR0_EL1 feature_register = Aarch64::ID_AA64MMFR0_EL1::read();
tcr_el1.IPS = feature_register.PARange;
Aarch64_TCR_EL1::write(tcr_el1);
Aarch64::TCR_EL1::write(tcr_el1);
// Enable MMU in the system control register
Aarch64_SCTLR_EL1 sctlr_el1 = Aarch64_SCTLR_EL1::read();
Aarch64::SCTLR_EL1 sctlr_el1 = Aarch64::SCTLR_EL1::read();
sctlr_el1.M = 1; //Enable MMU
Aarch64_SCTLR_EL1::write(sctlr_el1);
Aarch64::SCTLR_EL1::write(sctlr_el1);
flush();
}