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Kernel: Rename Aarch64Registers -> Registers and add Aarch64 namespace

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James Mintram 2021-11-21 14:10:23 +00:00 • committed by Brian Gianforcaro
parent 271b9b8da3
commit 34709c8d39
4 changed files with 71 additions and 70 deletions
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26
Kernel/Prekernel/Arch/aarch64/PrekernelExceptions.cpp
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@ -5,7 +5,7 @@
*/
#include <Kernel/Arch/aarch64/Aarch64Asm.h>
#include <Kernel/Arch/aarch64/Aarch64Registers.h>
#include <Kernel/Arch/aarch64/Registers.h>
#include <Kernel/Prekernel/Arch/aarch64/Aarch64_asm_utils.h>
#include <Kernel/Prekernel/Arch/aarch64/Prekernel.h>
@ -18,16 +18,16 @@ namespace Prekernel {
static void drop_to_el2()
{
Aarch64_SCR_EL3 secure_configuration_register_el3 = {};
Aarch64::SCR_EL3 secure_configuration_register_el3 = {};
secure_configuration_register_el3.ST = 1; // Don't trap access to Counter-timer Physical Secure registers
secure_configuration_register_el3.RW = 1; // Lower level to use Aarch64
secure_configuration_register_el3.NS = 1; // Non-secure state
secure_configuration_register_el3.HCE = 1; // Enable Hypervisor instructions at all levels
Aarch64_SCR_EL3::write(secure_configuration_register_el3);
Aarch64::SCR_EL3::write(secure_configuration_register_el3);
Aarch64_SPSR_EL3 saved_program_status_register_el3 = {};
Aarch64::SPSR_EL3 saved_program_status_register_el3 = {};
// Mask (disable) all interrupts
saved_program_status_register_el3.A = 1;
@ -36,21 +36,21 @@ static void drop_to_el2()
saved_program_status_register_el3.D = 1;
// Indicate EL1 as exception origin mode (so we go back there)
saved_program_status_register_el3.M = Aarch64_SPSR_EL3::Mode::EL2t;
saved_program_status_register_el3.M = Aarch64::SPSR_EL3::Mode::EL2t;
// Set the register
Aarch64_SPSR_EL3::write(saved_program_status_register_el3);
Aarch64::SPSR_EL3::write(saved_program_status_register_el3);
// This will jump into os_start() below
enter_el2_from_el3();
}
static void drop_to_el1()
{
Aarch64_HCR_EL2 hypervisor_configuration_register_el2 = {};
Aarch64::HCR_EL2 hypervisor_configuration_register_el2 = {};
hypervisor_configuration_register_el2.RW = 1; // EL1 to use 64-bit mode
Aarch64_HCR_EL2::write(hypervisor_configuration_register_el2);
Aarch64::HCR_EL2::write(hypervisor_configuration_register_el2);
Aarch64_SPSR_EL2 saved_program_status_register_el2 = {};
Aarch64::SPSR_EL2 saved_program_status_register_el2 = {};
// Mask (disable) all interrupts
saved_program_status_register_el2.A = 1;
@ -58,15 +58,15 @@ static void drop_to_el1()
saved_program_status_register_el2.F = 1;
// Indicate EL1 as exception origin mode (so we go back there)
saved_program_status_register_el2.M = Aarch64_SPSR_EL2::Mode::EL1t;
saved_program_status_register_el2.M = Aarch64::SPSR_EL2::Mode::EL1t;
Aarch64_SPSR_EL2::write(saved_program_status_register_el2);
Aarch64::SPSR_EL2::write(saved_program_status_register_el2);
enter_el1_from_el2();
}
static void set_up_el1()
{
Aarch64_SCTLR_EL1 system_control_register_el1 = Aarch64_SCTLR_EL1::reset_value();
Aarch64::SCTLR_EL1 system_control_register_el1 = Aarch64::SCTLR_EL1::reset_value();
system_control_register_el1.UCT = 1; // Don't trap access to CTR_EL0
system_control_register_el1.nTWE = 1; // Don't trap WFE instructions
@ -77,7 +77,7 @@ static void set_up_el1()
system_control_register_el1.SA = 1; // Enable stack access alignment check for EL1
system_control_register_el1.A = 1; // Enable memory access alignment check
Aarch64_SCTLR_EL1::write(system_control_register_el1);
Aarch64::SCTLR_EL1::write(system_control_register_el1);
}
void drop_to_exception_level_1()