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Kernel: Rename Aarch64Registers -> Registers and add Aarch64 namespace

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James Mintram 2021-11-21 14:10:23 +00:00 • committed by Brian Gianforcaro
parent 271b9b8da3
commit 34709c8d39
4 changed files with 71 additions and 70 deletions
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32
Kernel/Prekernel/Arch/aarch64/PrekernelMMU.cpp
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@ -9,7 +9,7 @@
#include <Kernel/Prekernel/Arch/aarch64/Prekernel.h>
#include <Kernel/Arch/aarch64/Aarch64Asm.h>
#include <Kernel/Arch/aarch64/Aarch64Registers.h>
#include <Kernel/Arch/aarch64/Registers.h>
#include <Kernel/Prekernel/Arch/aarch64/UART.h>
// Documentation here for Aarch64 Address Translations
@ -114,35 +114,35 @@ static void switch_to_page_table(u8* page_table)
static void activate_mmu()
{
Aarch64_MAIR_EL1 mair_el1 = {};
Aarch64::MAIR_EL1 mair_el1 = {};
mair_el1.Attr[0] = 0xFF; // Normal memory
mair_el1.Attr[1] = 0b00000100; // Device-nGnRE memory (non-cacheble)
Aarch64_MAIR_EL1::write(mair_el1);
Aarch64::MAIR_EL1::write(mair_el1);
// Configure cacheability attributes for memory associated with translation table walks
Aarch64_TCR_EL1 tcr_el1 = {};
Aarch64::TCR_EL1 tcr_el1 = {};
tcr_el1.SH1 = Aarch64_TCR_EL1::InnerShareable;
tcr_el1.ORGN1 = Aarch64_TCR_EL1::NormalMemory_Outer_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.IRGN1 = Aarch64_TCR_EL1::NormalMemory_Inner_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.SH1 = Aarch64::TCR_EL1::InnerShareable;
tcr_el1.ORGN1 = Aarch64::TCR_EL1::NormalMemory_Outer_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.IRGN1 = Aarch64::TCR_EL1::NormalMemory_Inner_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.SH0 = Aarch64_TCR_EL1::InnerShareable;
tcr_el1.ORGN0 = Aarch64_TCR_EL1::NormalMemory_Outer_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.IRGN0 = Aarch64_TCR_EL1::NormalMemory_Inner_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.SH0 = Aarch64::TCR_EL1::InnerShareable;
tcr_el1.ORGN0 = Aarch64::TCR_EL1::NormalMemory_Outer_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.IRGN0 = Aarch64::TCR_EL1::NormalMemory_Inner_WriteBack_ReadAllocate_WriteAllocateCacheable;
tcr_el1.TG1 = Aarch64_TCR_EL1::TG1GranuleSize::Size_4KB;
tcr_el1.TG0 = Aarch64_TCR_EL1::TG0GranuleSize::Size_4KB;
tcr_el1.TG1 = Aarch64::TCR_EL1::TG1GranuleSize::Size_4KB;
tcr_el1.TG0 = Aarch64::TCR_EL1::TG0GranuleSize::Size_4KB;
// Auto detect the Intermediate Physical Address Size
Aarch64_ID_AA64MMFR0_EL1 feature_register = Aarch64_ID_AA64MMFR0_EL1::read();
Aarch64::ID_AA64MMFR0_EL1 feature_register = Aarch64::ID_AA64MMFR0_EL1::read();
tcr_el1.IPS = feature_register.PARange;
Aarch64_TCR_EL1::write(tcr_el1);
Aarch64::TCR_EL1::write(tcr_el1);
// Enable MMU in the system control register
Aarch64_SCTLR_EL1 sctlr_el1 = Aarch64_SCTLR_EL1::read();
Aarch64::SCTLR_EL1 sctlr_el1 = Aarch64::SCTLR_EL1::read();
sctlr_el1.M = 1; //Enable MMU
Aarch64_SCTLR_EL1::write(sctlr_el1);
Aarch64::SCTLR_EL1::write(sctlr_el1);
flush();
}