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Kernel: Provide better types in MIDR register accessor for Aarch64
This avoids unnecessary and-masks during reading.
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1 changed files with 5 additions and 5 deletions
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@ -700,11 +700,11 @@ static_assert(sizeof(SCTLR_EL1) == 8);
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// https://developer.arm.com/documentation/ddi0601/2022-09/AArch64-Registers/MIDR-EL1--Main-ID-Register?lang=en
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// MIDR_EL1, Main ID Register
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struct alignas(u64) MIDR_EL1 {
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int Revision : 4;
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int PartNum : 12;
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int Architecture : 4;
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int Variant : 4;
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int Implementer : 8;
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u8 Revision : 4;
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u16 PartNum : 12;
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u8 Architecture : 4;
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u8 Variant : 4;
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u8 Implementer : 8;
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int : 32;
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static inline MIDR_EL1 read()
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