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Kernel: Add MIDR_EL1, Main ID Register

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This register is already provided in a separate class
but will be migrated here for uniform access
This commit is contained in:
konrad 2022-12-24 01:19:35 +01:00 • committed by Andreas Kling
parent d0b73352cc
commit e7d4bbcde8
1 changed files with 22 additions and 0 deletions
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22
Kernel/Arch/aarch64/Registers.h
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@ -311,6 +311,28 @@ struct alignas(u64) SCTLR_EL1 {
}; };
static_assert(sizeof(SCTLR_EL1) == 8); static_assert(sizeof(SCTLR_EL1) == 8);
// https://developer.arm.com/documentation/ddi0601/2022-09/AArch64-Registers/MIDR-EL1--Main-ID-Register?lang=en
// MIDR_EL1, Main ID Register
struct alignas(u64) MIDR_EL1 {
int Revision : 4;
int PartNum : 12;
int Architecture : 4;
int Variant : 4;
int Implementer : 8;
int : 32;
static inline MIDR_EL1 read()
{
MIDR_EL1 affinity_register;
asm("mrs %[value], MIDR_EL1"
: [value] "=r"(affinity_register));
return affinity_register;
}
};
static_assert(sizeof(MIDR_EL1) == 8);
// https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/HCR-EL2--Hypervisor-Configuration-Register // https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/HCR-EL2--Hypervisor-Configuration-Register
// Hypervisor Configuration Register // Hypervisor Configuration Register
struct alignas(u64) HCR_EL2 { struct alignas(u64) HCR_EL2 {