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Kernel: Move Prekernel{CPU, Exceptions}.cpp out of Prekernel directory
This lets us delete the Prekernel.h file, and gets us closer to deleting the Prekernel from the aarch64 Kernel.
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7 changed files with 11 additions and 20 deletions
199
Kernel/Arch/aarch64/MMU.cpp
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199
Kernel/Arch/aarch64/MMU.cpp
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/*
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* Copyright (c) 2021, James Mintram <me@jamesrm.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <AK/Types.h>
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#include <Kernel/Arch/aarch64/CPU.h>
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#include <Kernel/Arch/aarch64/ASM_wrapper.h>
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#include <Kernel/Arch/aarch64/RPi/MMIO.h>
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#include <Kernel/Arch/aarch64/RPi/UART.h>
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#include <Kernel/Arch/aarch64/Registers.h>
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#include <Kernel/Panic.h>
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// Documentation here for Aarch64 Address Translations
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// https://documentation-service.arm.com/static/5efa1d23dbdee951c1ccdec5?token=
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using namespace Kernel;
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// These come from the linker script
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extern u8 page_tables_phys_start[];
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extern u8 page_tables_phys_end[];
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namespace Prekernel {
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// physical memory
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constexpr u32 START_OF_NORMAL_MEMORY = 0x00000000;
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constexpr u32 END_OF_NORMAL_MEMORY = 0x3EFFFFFF;
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// 4KiB page size was chosen for the prekernel to make this code slightly simpler
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constexpr u32 GRANULE_SIZE = 0x1000;
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constexpr u32 PAGE_TABLE_SIZE = 0x1000;
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// Documentation for translation table format
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// https://developer.arm.com/documentation/101811/0101/Controlling-address-translation
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constexpr u32 PAGE_DESCRIPTOR = 0b11;
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constexpr u32 TABLE_DESCRIPTOR = 0b11;
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constexpr u32 DESCRIPTOR_MASK = ~0b11;
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constexpr u32 ACCESS_FLAG = 1 << 10;
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// shareability
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constexpr u32 OUTER_SHAREABLE = (2 << 8);
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constexpr u32 INNER_SHAREABLE = (3 << 8);
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// these index into the MAIR attribute table
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constexpr u32 NORMAL_MEMORY = (0 << 2);
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constexpr u32 DEVICE_MEMORY = (1 << 2);
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ALWAYS_INLINE static u64* descriptor_to_pointer(FlatPtr descriptor)
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{
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return (u64*)(descriptor & DESCRIPTOR_MASK);
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}
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namespace {
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class PageBumpAllocator {
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public:
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PageBumpAllocator(u64* start, u64* end)
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: m_start(start)
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, m_end(end)
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, m_current(start)
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{
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if (m_start >= m_end) {
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PANIC("Invalid memory range passed to PageBumpAllocator");
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}
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if ((FlatPtr)m_start % PAGE_TABLE_SIZE != 0 || (FlatPtr)m_end % PAGE_TABLE_SIZE != 0) {
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PANIC("Memory range passed into PageBumpAllocator not aligned to PAGE_TABLE_SIZE");
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}
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}
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u64* take_page()
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{
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if (m_current == m_end) {
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PANIC("Prekernel pagetable memory exhausted");
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}
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u64* page = m_current;
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m_current += (PAGE_TABLE_SIZE / sizeof(FlatPtr));
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zero_page(page);
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return page;
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}
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private:
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void zero_page(u64* page)
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{
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// Memset all page table memory to zero
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for (u64* p = page; p < page + (PAGE_TABLE_SIZE / sizeof(u64)); p++) {
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*p = 0;
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}
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}
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u64 const* m_start;
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u64 const* m_end;
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u64* m_current;
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};
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}
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static void insert_identity_entries_for_physical_memory_range(PageBumpAllocator& allocator, u64* page_table, FlatPtr start, FlatPtr end, u64 flags)
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{
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// Not very efficient, but simple and it works.
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for (FlatPtr addr = start; addr < end; addr += GRANULE_SIZE) {
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// Each level has 9 bits (512 entries)
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u64 level0_idx = (addr >> 39) & 0x1FF;
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u64 level1_idx = (addr >> 30) & 0x1FF;
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u64 level2_idx = (addr >> 21) & 0x1FF;
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u64 level3_idx = (addr >> 12) & 0x1FF;
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u64* level1_table = page_table;
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if (level1_table[level0_idx] == 0) {
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level1_table[level0_idx] = (FlatPtr)allocator.take_page();
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level1_table[level0_idx] |= TABLE_DESCRIPTOR;
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}
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u64* level2_table = descriptor_to_pointer(level1_table[level0_idx]);
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if (level2_table[level1_idx] == 0) {
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level2_table[level1_idx] = (FlatPtr)allocator.take_page();
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level2_table[level1_idx] |= TABLE_DESCRIPTOR;
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}
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u64* level3_table = descriptor_to_pointer(level2_table[level1_idx]);
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if (level3_table[level2_idx] == 0) {
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level3_table[level2_idx] = (FlatPtr)allocator.take_page();
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level3_table[level2_idx] |= TABLE_DESCRIPTOR;
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}
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u64* level4_table = descriptor_to_pointer(level3_table[level2_idx]);
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u64* l4_entry = &level4_table[level3_idx];
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*l4_entry = addr;
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*l4_entry |= flags;
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}
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}
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static void build_identity_map(PageBumpAllocator& allocator)
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{
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u64* level1_table = allocator.take_page();
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u64 normal_memory_flags = ACCESS_FLAG | PAGE_DESCRIPTOR | INNER_SHAREABLE | NORMAL_MEMORY;
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u64 device_memory_flags = ACCESS_FLAG | PAGE_DESCRIPTOR | OUTER_SHAREABLE | DEVICE_MEMORY;
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insert_identity_entries_for_physical_memory_range(allocator, level1_table, START_OF_NORMAL_MEMORY, END_OF_NORMAL_MEMORY, normal_memory_flags);
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insert_identity_entries_for_physical_memory_range(allocator, level1_table, MMIO::the().peripheral_base_address(), MMIO::the().peripheral_end_address(), device_memory_flags);
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}
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static void switch_to_page_table(u8* page_table)
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{
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Aarch64::Asm::set_ttbr0_el1((FlatPtr)page_table);
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Aarch64::Asm::set_ttbr1_el1((FlatPtr)page_table);
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}
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static void activate_mmu()
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{
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Aarch64::MAIR_EL1 mair_el1 = {};
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mair_el1.Attr[0] = 0xFF; // Normal memory
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mair_el1.Attr[1] = 0b00000100; // Device-nGnRE memory (non-cacheble)
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Aarch64::MAIR_EL1::write(mair_el1);
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// Configure cacheability attributes for memory associated with translation table walks
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Aarch64::TCR_EL1 tcr_el1 = {};
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tcr_el1.SH1 = Aarch64::TCR_EL1::InnerShareable;
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tcr_el1.ORGN1 = Aarch64::TCR_EL1::NormalMemory_Outer_WriteBack_ReadAllocate_WriteAllocateCacheable;
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tcr_el1.IRGN1 = Aarch64::TCR_EL1::NormalMemory_Inner_WriteBack_ReadAllocate_WriteAllocateCacheable;
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tcr_el1.SH0 = Aarch64::TCR_EL1::InnerShareable;
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tcr_el1.ORGN0 = Aarch64::TCR_EL1::NormalMemory_Outer_WriteBack_ReadAllocate_WriteAllocateCacheable;
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tcr_el1.IRGN0 = Aarch64::TCR_EL1::NormalMemory_Inner_WriteBack_ReadAllocate_WriteAllocateCacheable;
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tcr_el1.TG1 = Aarch64::TCR_EL1::TG1GranuleSize::Size_4KB;
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tcr_el1.TG0 = Aarch64::TCR_EL1::TG0GranuleSize::Size_4KB;
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// Auto detect the Intermediate Physical Address Size
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Aarch64::ID_AA64MMFR0_EL1 feature_register = Aarch64::ID_AA64MMFR0_EL1::read();
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tcr_el1.IPS = feature_register.PARange;
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Aarch64::TCR_EL1::write(tcr_el1);
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// Enable MMU in the system control register
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Aarch64::SCTLR_EL1 sctlr_el1 = Aarch64::SCTLR_EL1::read();
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sctlr_el1.M = 1; // Enable MMU
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Aarch64::SCTLR_EL1::write(sctlr_el1);
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Aarch64::Asm::flush();
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}
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void init_prekernel_page_tables()
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{
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PageBumpAllocator allocator((u64*)page_tables_phys_start, (u64*)page_tables_phys_end);
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build_identity_map(allocator);
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switch_to_page_table(page_tables_phys_start);
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activate_mmu();
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}
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}
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