mirror of
https://github.com/RGBCube/serenity
synced 2025-07-09 04:17:35 +00:00
398d271a46
About half of the Processor code is common across architectures, so let's share it with a templated base class. Also, other code that can be shared in some ways, like FPUState and TrapFrame functions, is adjusted here. Functions which cannot be shared trivially (without internal refactoring) are left alone for now.
147 lines
3.5 KiB
C++
147 lines
3.5 KiB
C++
/*
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* Copyright (c) 2021, James Mintram <me@jamesrm.com>
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* Copyright (c) 2021, Nico Weber <thakis@chromium.org>
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* Copyright (c) 2021, Marcin Undak <mcinek@gmail.com>
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* Copyright (c) 2021, Jesse Buhagiar <jooster669@gmail.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <Kernel/Arch/Processor.h>
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#include <Kernel/Arch/aarch64/Registers.h>
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namespace Kernel::Aarch64::Asm {
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inline void set_ttbr1_el1(FlatPtr ttbr1_el1)
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{
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asm volatile("msr ttbr1_el1, %[value]" ::[value] "r"(ttbr1_el1));
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}
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inline void set_ttbr0_el1(FlatPtr ttbr0_el1)
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{
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asm volatile("msr ttbr0_el1, %[value]" ::[value] "r"(ttbr0_el1));
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}
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inline FlatPtr get_ttbr0_el1()
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{
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FlatPtr ttbr0_el1;
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asm volatile("mrs %[value], ttbr0_el1\n"
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: [value] "=r"(ttbr0_el1));
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return ttbr0_el1;
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}
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inline void set_sp_el1(FlatPtr sp_el1)
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{
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asm volatile("msr sp_el1, %[value]" ::[value] "r"(sp_el1));
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}
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inline void set_tpidr_el0(FlatPtr tpidr_el0)
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{
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asm volatile("msr tpidr_el0, %[value]" ::[value] "r"(tpidr_el0));
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}
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inline void flush()
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{
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asm volatile("dsb ish");
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asm volatile("isb");
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}
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[[noreturn]] inline void halt()
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{
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for (;;) {
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asm volatile("wfi");
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}
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}
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enum class ExceptionLevel : u8 {
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EL0 = 0,
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EL1 = 1,
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EL2 = 2,
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EL3 = 3,
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};
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inline ExceptionLevel get_current_exception_level()
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{
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u64 current_exception_level;
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asm volatile("mrs %[value], CurrentEL"
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: [value] "=r"(current_exception_level));
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current_exception_level = (current_exception_level >> 2) & 0x3;
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return static_cast<ExceptionLevel>(current_exception_level);
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}
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inline void wait_cycles(int n)
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{
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// FIXME: Make timer-based.
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for (int i = 0; i < n; i = i + 1) {
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Processor::pause();
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}
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}
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inline void load_el1_vector_table(void* vector_table)
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{
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asm volatile("msr VBAR_EL1, %[value]" ::[value] "r"(vector_table));
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}
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inline void enter_el2_from_el3()
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{
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// NOTE: This also copies the current stack pointer into SP_EL2, as
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// the processor is set up to use SP_EL2 when jumping into EL2.
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asm volatile(" mov x0, sp\n"
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" msr sp_el2, x0\n"
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" adr x0, entered_el2\n"
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" msr elr_el3, x0\n"
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" eret\n"
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"entered_el2:" ::
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: "x0");
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}
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inline void enter_el1_from_el2()
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{
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// NOTE: This also copies the current stack pointer into SP_EL1, as
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// the processor is set up to use SP_EL1 when jumping into EL1.
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asm volatile(" mov x0, sp\n"
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" msr sp_el1, x0\n"
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" adr x0, entered_el1\n"
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" msr elr_el2, x0\n"
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" eret\n"
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"entered_el1:" ::
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: "x0");
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}
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inline u64 read_rndrrs()
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{
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u64 value = 0;
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asm volatile(
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"retry:\n"
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"mrs %[value], s3_3_c2_c4_1 \n" // encoded RNDRRS register
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"b.eq retry\n"
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: [value] "=r"(value));
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return value;
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}
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inline FlatPtr get_cache_line_size()
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{
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FlatPtr ctr_el0;
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asm volatile("mrs %[value], ctr_el0"
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: [value] "=r"(ctr_el0));
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auto log2_size = (ctr_el0 >> 16) & 0xF;
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return 1 << log2_size;
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}
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inline void flush_data_cache(FlatPtr start, size_t size)
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{
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auto const cache_size = get_cache_line_size();
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for (FlatPtr addr = align_down_to(start, cache_size); addr < start + size; addr += cache_size)
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asm volatile("dc civac, %[addr]" ::[addr] "r"(addr)
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: "memory");
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asm volatile("dsb sy" ::
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: "memory");
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}
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}
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