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14 commits

Author SHA1 Message Date
kleines Filmröllchen
398d271a46 Kernel: Share Processor class (and others) across architectures
About half of the Processor code is common across architectures, so
let's share it with a templated base class. Also, other code that can be
shared in some ways, like FPUState and TrapFrame functions, is adjusted
here. Functions which cannot be shared trivially (without internal
refactoring) are left alone for now.
2023-10-03 16:08:29 -06:00
Daniel Bertalan
3d383974cd Kernel: Flush data cache before passing a buffer to the VC Mailbox
Otherwise, the message's contents might be in the cache only, so
VideoCore will read stale/garbage data from main memory.

This fixes framebuffer setup on bare metal with the data cache enabled.
2023-05-17 01:38:03 -06:00
Timon Kruiper
baa5cb9e30 Kernel/aarch64: Add volatile modifier to various asm statements
This prevents the optimizer from reordering them, which hopefully
prevents future bugs.
2023-04-13 20:22:08 +02:00
Timon Kruiper
cfd73e5d9f Kernel/aarch64: Implement Thread Local Storage
This commit adds Processor::set_thread_specific_data, and this function
is used to factor out architecture specific implementation of setting
the thread specific data. This function is implemented for
aarch64 and x86_64, and the callsites are changed to use this function
instead.
2023-02-15 22:53:19 +01:00
Timon Kruiper
9e90932bfb Kernel/aarch64: Add helper to get the current TTBR0_EL1 2023-01-27 11:41:43 +01:00
Timon Kruiper
247109cee6 Kernel/aarch64: Execute kernel with SP_EL1 instead of SP_EL0
Until now the kernel was always executing with SP_EL0, as this made the
initial dropping to EL1 a bit easier. This commit changes this behaviour
to use the corresponding SP_ELx for each exception level.

To make sure that the execution of the C++ code can continue, the
current stack pointer is copied into the corresponding SP_ELx just
before dropping an exception level.
2023-01-27 11:41:43 +01:00
konrad
e1c50b83e1 Kernel: Use RDSEED assembly snippet to seed RNG on Aarch64
There’s similar RDRAND register (encoded as ‘s3_3_c2_c4_0ʼ) to be
added if needed. RNG CPU feature on Aarch64 guarantees existence of both
RDSEED and RDRAND registers simultaneously—in contrast to x86-64, where
respective instructions are independent of each other.
2023-01-25 23:17:36 +01:00
konrad
0f81fb03f2 Kernel: Introduce stages in Aarch64 CPU initialization phase
Dropping to each exception level is now more explicit.
2023-01-18 22:58:42 +01:00
Nico Weber
7f4680a377 Kernel/aarch64: Remove counterproductive volatile
Should not be needed, and triggers -Wvolatile in gcc.
See discussion on #16790.
2023-01-05 19:45:27 +01:00
kleines Filmröllchen
5d00e21852 Kernel/aarch64: Implement wait_cycles as a pause loop
The hand-written assembly does not compile under Clang due to register
size mismatches. Using a loop is slower (~6 instructions on O2 as
opposed to 2 with hand-written assembly), but using the pause
instruction makes this more efficient even under TCG.
2022-12-30 08:32:46 -07:00
Gunnar Beutner
056e406a12 Kernel: Add even more AARCH64 stubs 2022-10-18 13:08:25 +02:00
Timon Kruiper
06432719fd Kernel: Set up initial exception stack when going into EL1 on aarch64
When an exception is triggered on aarch64, the processor always switches
to the exception stack which is defined by the SP_EL1 register.
2022-05-21 20:23:32 +01:00
Timon Kruiper
e7c5fd978b Kernel: Move Prekernel assembly utils to aarch64/ASM_wrapper.h
By moving these functions to the ASM_wrapper.h file, we can get rid of
another Prekernel file.
2022-05-12 23:14:05 +02:00
James Mintram
4a4a3193f8 Kernel: Rename Aarch64Asm -> ASM_wrapper and add Aarch64::Asm namespace 2021-11-28 22:01:21 -08:00
Renamed from Kernel/Arch/aarch64/Aarch64Asm.h (Browse further)