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aca317d889
PCI MMIO access is done by modifying the related PhysicalPage directly, then we request to remap the region to create the mapping.
230 lines
9.2 KiB
C++
230 lines
9.2 KiB
C++
/*
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* Copyright (c) 2018-2020, Andreas Kling <kling@serenityos.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <AK/Optional.h>
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#include <Kernel/IO.h>
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#include <Kernel/PCI/MMIOAccess.h>
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#include <Kernel/VM/MemoryManager.h>
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#define PCI_MMIO_CONFIG_SPACE_SIZE 4096
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uint32_t PCI::MMIOAccess::get_segments_count()
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{
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return m_segments.size();
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}
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uint8_t PCI::MMIOAccess::get_segment_start_bus(u32 seg)
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{
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ASSERT(m_segments.contains(seg));
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return m_segments.get(seg).value()->get_start_bus();
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}
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uint8_t PCI::MMIOAccess::get_segment_end_bus(u32 seg)
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{
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ASSERT(m_segments.contains(seg));
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return m_segments.get(seg).value()->get_end_bus();
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}
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void PCI::MMIOAccess::initialize(ACPI_RAW::MCFG& mcfg)
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{
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if (!PCI::Access::is_initialized())
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new PCI::MMIOAccess(mcfg);
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}
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PCI::MMIOAccess::MMIOAccess(ACPI_RAW::MCFG& raw_mcfg)
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: m_mcfg(raw_mcfg)
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, m_segments(*new HashMap<u16, MMIOSegment*>())
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, m_mapped_address(ChangeableAddress(0xFFFF, 0xFF, 0xFF, 0xFF))
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{
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kprintf("PCI: Using MMIO Mechanism for PCI Configuartion Space Access\n");
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m_mmio_window_region = MM.allocate_kernel_region(PAGE_ROUND_UP(PCI_MMIO_CONFIG_SPACE_SIZE), "PCI MMIO", Region::Access::Read | Region::Access::Write);
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auto checkup_region = MM.allocate_kernel_region(PhysicalAddress(page_base_of((u32)&raw_mcfg)),(PAGE_SIZE * 2), "PCI MCFG Checkup", Region::Access::Read | Region::Access::Write);
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Checking MCFG Table length to choose the correct mapping size\n");
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#endif
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ACPI_RAW::SDTHeader* sdt = (ACPI_RAW::SDTHeader*)checkup_region->vaddr().offset(offset_in_page((u32)&raw_mcfg)).as_ptr();
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u32 length = sdt->length;
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u8 revision = sdt->revision;
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kprintf("PCI: MCFG, length - %u, revision %d\n", length, revision);
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checkup_region->unmap();
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auto mcfg_region = MM.allocate_kernel_region(PhysicalAddress(page_base_of((u32)&raw_mcfg)), PAGE_ROUND_UP(length) + PAGE_SIZE, "PCI Parsing MCFG", Region::Access::Read | Region::Access::Write);
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auto& mcfg = *(ACPI_RAW::MCFG*)mcfg_region->vaddr().offset(offset_in_page((u32)&raw_mcfg)).as_ptr();
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Checking MCFG @ V 0x%x, P 0x%x\n", &mcfg, &raw_mcfg);
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#endif
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for (u32 index = 0; index < ((mcfg.header.length - sizeof(ACPI_RAW::MCFG)) / sizeof(ACPI_RAW::PCI_MMIO_Descriptor)); index++) {
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u8 start_bus = mcfg.descriptors[index].start_pci_bus;
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u8 end_bus = mcfg.descriptors[index].end_pci_bus;
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u32 lower_addr = mcfg.descriptors[index].base_addr;
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m_segments.set(index, new PCI::MMIOSegment(PhysicalAddress(lower_addr), start_bus, end_bus));
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kprintf("PCI: New PCI segment @ P 0x%x, PCI buses (%d-%d)\n", lower_addr, start_bus, end_bus);
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}
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mcfg_region->unmap();
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kprintf("PCI: MMIO segments - %d\n", m_segments.size());
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InterruptDisabler disabler;
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#ifdef PCI_DEBUG
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dbgprintf("PCI: mapped address (%w:%b:%b.%b)\n", m_mapped_address.seg(), m_mapped_address.bus(), m_mapped_address.slot(), m_mapped_address.function());
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#endif
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map_device(Address(0, 0, 0, 0));
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Default mapped address (%w:%b:%b.%b)\n", m_mapped_address.seg(), m_mapped_address.bus(), m_mapped_address.slot(), m_mapped_address.function());
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#endif
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}
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void PCI::MMIOAccess::map_device(Address address)
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{
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if (m_mapped_address == address)
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return;
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// FIXME: Map and put some lock!
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ASSERT_INTERRUPTS_DISABLED();
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ASSERT(m_segments.contains(address.seg()));
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auto segment = m_segments.get(address.seg());
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PhysicalAddress segment_lower_addr = segment.value()->get_paddr();
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PhysicalAddress device_physical_mmio_space = segment_lower_addr.offset(
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PCI_MMIO_CONFIG_SPACE_SIZE * address.function() + (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE) * address.slot() + (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE * PCI_MAX_DEVICES_PER_BUS) * (address.bus() - segment.value()->get_start_bus()));
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Mapping device @ pci (%w:%b:%b.%b), V 0x%x, P 0x%x\n", address.seg(), address.bus(), address.slot(), address.function(), m_mmio_window_region->vaddr().get(), device_physical_mmio_space.get());
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#endif
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m_mmio_window_region->vmobject().physical_pages()[0] = PhysicalPage::create(device_physical_mmio_space,false,false);
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m_mmio_window_region->remap();
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m_mapped_address = address;
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}
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u8 PCI::MMIOAccess::read8_field(Address address, u32 field)
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{
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InterruptDisabler disabler;
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ASSERT(field <= 0xfff);
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Reading field %u, Address(%w:%b:%b.%b)\n", field, address.seg(), address.bus(), address.slot(), address.function());
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#endif
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map_device(address);
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return *((u8*)(m_mmio_window_region->vaddr().get() + (field & 0xfff)));
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}
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u16 PCI::MMIOAccess::read16_field(Address address, u32 field)
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{
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InterruptDisabler disabler;
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ASSERT(field < 0xfff);
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Reading field %u, Address(%w:%b:%b.%b)\n", field, address.seg(), address.bus(), address.slot(), address.function());
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#endif
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map_device(address);
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return *((u16*)(m_mmio_window_region->vaddr().get() + (field & 0xfff)));
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}
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u32 PCI::MMIOAccess::read32_field(Address address, u32 field)
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{
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InterruptDisabler disabler;
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ASSERT(field <= 0xffc);
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Reading field %u, Address(%w:%b:%b.%b)\n", field, address.seg(), address.bus(), address.slot(), address.function());
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#endif
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map_device(address);
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return *((u32*)(m_mmio_window_region->vaddr().get() + (field & 0xfff)));
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}
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void PCI::MMIOAccess::write8_field(Address address, u32 field, u8 value)
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{
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InterruptDisabler disabler;
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ASSERT(field <= 0xfff);
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Write to field %u, Address(%w:%b:%b.%b), value 0x%x\n", field, address.seg(), address.bus(), address.slot(), address.function(), value);
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#endif
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map_device(address);
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*((u8*)(m_mmio_window_region->vaddr().get() + (field & 0xfff))) = value;
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}
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void PCI::MMIOAccess::write16_field(Address address, u32 field, u16 value)
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{
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InterruptDisabler disabler;
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ASSERT(field < 0xfff);
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Write to field %u, Address(%w:%b:%b.%b), value 0x%x\n", field, address.seg(), address.bus(), address.slot(), address.function(), value);
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#endif
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map_device(address);
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*((u16*)(m_mmio_window_region->vaddr().get() + (field & 0xfff))) = value;
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}
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void PCI::MMIOAccess::write32_field(Address address, u32 field, u32 value)
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{
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InterruptDisabler disabler;
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ASSERT(field <= 0xffc);
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Write to field %u, Address(%w:%b:%b.%b), value 0x%x\n", field, address.seg(), address.bus(), address.slot(), address.function(), value);
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#endif
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map_device(address);
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*((u32*)(m_mmio_window_region->vaddr().get() + (field & 0xfff))) = value;
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}
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void PCI::MMIOAccess::enumerate_all(Function<void(Address, ID)>& callback)
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{
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for (u16 seg = 0; seg < m_segments.size(); seg++) {
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Enumerating Memory mapped IO segment %u\n", seg);
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#endif
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// Single PCI host controller.
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if ((read8_field(Address(seg), PCI_HEADER_TYPE) & 0x80) == 0) {
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enumerate_bus(-1, 0, callback);
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return;
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}
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// Multiple PCI host controllers.
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for (u8 function = 0; function < 8; ++function) {
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if (read16_field(Address(seg, 0, 0, function), PCI_VENDOR_ID) == PCI_NONE)
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break;
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enumerate_bus(-1, function, callback);
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}
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}
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}
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PCI::MMIOSegment::MMIOSegment(PhysicalAddress segment_base_addr, u8 start_bus, u8 end_bus)
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: m_base_addr(segment_base_addr)
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, m_start_bus(start_bus)
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, m_end_bus(end_bus)
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{
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}
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u8 PCI::MMIOSegment::get_start_bus()
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{
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return m_start_bus;
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}
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u8 PCI::MMIOSegment::get_end_bus()
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{
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return m_end_bus;
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}
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size_t PCI::MMIOSegment::get_size()
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{
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return (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE * PCI_MAX_DEVICES_PER_BUS * (get_end_bus() - get_start_bus()));
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}
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PhysicalAddress PCI::MMIOSegment::get_paddr()
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{
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return m_base_addr;
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}
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