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Kernel/PCI: Hold a reference to DeviceIdentifier in the Device class
There are now 2 separate classes for almost the same object type: - EnumerableDeviceIdentifier, which is used in the enumeration code for all PCI host controller classes. This is allowed to be moved and copied, as it doesn't support ref-counting. - DeviceIdentifier, which inherits from EnumerableDeviceIdentifier. This class uses ref-counting, and is not allowed to be copied. It has a spinlock member in its structure to allow safely executing complicated IO sequences on a PCI device and its space configuration. There's a static method that allows a quick conversion from EnumerableDeviceIdentifier to DeviceIdentifier while creating a NonnullRefPtr out of it. The reason for doing this is for the sake of integrity and reliablity of the system in 2 places: - Ensure that "complicated" tasks that rely on manipulating PCI device registers are done in a safe manner. For example, determining a PCI BAR space size requires multiple read and writes to the same register, and if another CPU tries to do something else with our selected register, then the result will be a catastrophe. - Allow the PCI API to have a united form around a shared object which actually holds much more data than the PCI::Address structure. This is fundamental if we want to do certain types of optimizations, and be able to support more features of the PCI bus in the foreseeable future. This patch already has several implications: - All PCI::Device(s) hold a reference to a DeviceIdentifier structure being given originally from the PCI::Access singleton. This means that all instances of DeviceIdentifier structures are located in one place, and all references are pointing to that location. This ensures that locking the operation spinlock will take effect in all the appropriate places. - We no longer support adding PCI host controllers and then immediately allow for enumerating it with a lambda function. It was found that this method is extremely broken and too much complicated to work reliably with the new paradigm being introduced in this patch. This means that for Volume Management Devices (Intel VMD devices), we simply first enumerate the PCI bus for such devices in the storage code, and if we find a device, we attach it in the PCI::Access method which will scan for devices behind that bridge and will add new DeviceIdentifier(s) objects to its internal Vector. Afterwards, we just continue as usual with scanning for actual storage controllers, so we will find a corresponding NVMe controllers if there were any behind that VMD bridge.
This commit is contained in:
Liav A
Jelle Raaijmakers
parent
3226ce3d83
commit
1f9d3a3523
39 changed files with 493 additions and 390 deletions
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@ -10,106 +10,141 @@
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namespace Kernel::PCI {
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void write8(Address address, PCI::RegisterOffset field, u8 value) { Access::the().write8_field(address, to_underlying(field), value); }
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void write16(Address address, PCI::RegisterOffset field, u16 value) { Access::the().write16_field(address, to_underlying(field), value); }
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void write32(Address address, PCI::RegisterOffset field, u32 value) { Access::the().write32_field(address, to_underlying(field), value); }
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u8 read8(Address address, PCI::RegisterOffset field) { return Access::the().read8_field(address, to_underlying(field)); }
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u16 read16(Address address, PCI::RegisterOffset field) { return Access::the().read16_field(address, to_underlying(field)); }
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u32 read32(Address address, PCI::RegisterOffset field) { return Access::the().read32_field(address, to_underlying(field)); }
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void write8_locked(DeviceIdentifier const& identifier, PCI::RegisterOffset field, u8 value)
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{
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VERIFY(identifier.operation_lock().is_locked());
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Access::the().write8_field(identifier, to_underlying(field), value);
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}
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void write16_locked(DeviceIdentifier const& identifier, PCI::RegisterOffset field, u16 value)
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{
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VERIFY(identifier.operation_lock().is_locked());
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Access::the().write16_field(identifier, to_underlying(field), value);
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}
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void write32_locked(DeviceIdentifier const& identifier, PCI::RegisterOffset field, u32 value)
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{
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VERIFY(identifier.operation_lock().is_locked());
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Access::the().write32_field(identifier, to_underlying(field), value);
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}
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u8 read8_locked(DeviceIdentifier const& identifier, PCI::RegisterOffset field)
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{
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VERIFY(identifier.operation_lock().is_locked());
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return Access::the().read8_field(identifier, to_underlying(field));
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}
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u16 read16_locked(DeviceIdentifier const& identifier, PCI::RegisterOffset field)
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{
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VERIFY(identifier.operation_lock().is_locked());
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return Access::the().read16_field(identifier, to_underlying(field));
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}
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u32 read32_locked(DeviceIdentifier const& identifier, PCI::RegisterOffset field)
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{
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VERIFY(identifier.operation_lock().is_locked());
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return Access::the().read32_field(identifier, to_underlying(field));
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}
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ErrorOr<void> enumerate(Function<void(DeviceIdentifier const&)> callback)
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{
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return Access::the().fast_enumerate(callback);
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}
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DeviceIdentifier get_device_identifier(Address address)
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HardwareID get_hardware_id(DeviceIdentifier const& identifier)
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{
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return Access::the().get_device_identifier(address);
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SpinlockLocker locker(identifier.operation_lock());
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return { read16_locked(identifier, PCI::RegisterOffset::VENDOR_ID), read16_locked(identifier, PCI::RegisterOffset::DEVICE_ID) };
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}
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HardwareID get_hardware_id(Address address)
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void enable_io_space(DeviceIdentifier const& identifier)
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{
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return { read16(address, PCI::RegisterOffset::VENDOR_ID), read16(address, PCI::RegisterOffset::DEVICE_ID) };
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SpinlockLocker locker(identifier.operation_lock());
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write16_locked(identifier, PCI::RegisterOffset::COMMAND, read16_locked(identifier, PCI::RegisterOffset::COMMAND) | (1 << 0));
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}
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void disable_io_space(DeviceIdentifier const& identifier)
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{
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SpinlockLocker locker(identifier.operation_lock());
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write16_locked(identifier, PCI::RegisterOffset::COMMAND, read16_locked(identifier, PCI::RegisterOffset::COMMAND) & ~(1 << 0));
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}
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void enable_io_space(Address address)
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void enable_memory_space(DeviceIdentifier const& identifier)
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{
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write16(address, PCI::RegisterOffset::COMMAND, read16(address, PCI::RegisterOffset::COMMAND) | (1 << 0));
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SpinlockLocker locker(identifier.operation_lock());
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write16_locked(identifier, PCI::RegisterOffset::COMMAND, read16_locked(identifier, PCI::RegisterOffset::COMMAND) | (1 << 1));
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}
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void disable_io_space(Address address)
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void disable_memory_space(DeviceIdentifier const& identifier)
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{
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write16(address, PCI::RegisterOffset::COMMAND, read16(address, PCI::RegisterOffset::COMMAND) & ~(1 << 0));
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SpinlockLocker locker(identifier.operation_lock());
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write16_locked(identifier, PCI::RegisterOffset::COMMAND, read16_locked(identifier, PCI::RegisterOffset::COMMAND) & ~(1 << 1));
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}
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void enable_memory_space(Address address)
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bool is_io_space_enabled(DeviceIdentifier const& identifier)
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{
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write16(address, PCI::RegisterOffset::COMMAND, read16(address, PCI::RegisterOffset::COMMAND) | (1 << 1));
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}
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void disable_memory_space(Address address)
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{
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write16(address, PCI::RegisterOffset::COMMAND, read16(address, PCI::RegisterOffset::COMMAND) & ~(1 << 1));
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}
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bool is_io_space_enabled(Address address)
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{
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return (read16(address, PCI::RegisterOffset::COMMAND) & 1) != 0;
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SpinlockLocker locker(identifier.operation_lock());
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return (read16_locked(identifier, PCI::RegisterOffset::COMMAND) & 1) != 0;
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}
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void enable_interrupt_line(Address address)
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void enable_interrupt_line(DeviceIdentifier const& identifier)
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{
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write16(address, PCI::RegisterOffset::COMMAND, read16(address, PCI::RegisterOffset::COMMAND) & ~(1 << 10));
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SpinlockLocker locker(identifier.operation_lock());
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write16_locked(identifier, PCI::RegisterOffset::COMMAND, read16_locked(identifier, PCI::RegisterOffset::COMMAND) & ~(1 << 10));
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}
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void disable_interrupt_line(Address address)
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void disable_interrupt_line(DeviceIdentifier const& identifier)
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{
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write16(address, PCI::RegisterOffset::COMMAND, read16(address, PCI::RegisterOffset::COMMAND) | 1 << 10);
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SpinlockLocker locker(identifier.operation_lock());
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write16_locked(identifier, PCI::RegisterOffset::COMMAND, read16_locked(identifier, PCI::RegisterOffset::COMMAND) | 1 << 10);
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}
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u32 get_BAR0(Address address)
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u32 get_BAR0(DeviceIdentifier const& identifier)
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{
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return read32(address, PCI::RegisterOffset::BAR0);
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SpinlockLocker locker(identifier.operation_lock());
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return read32_locked(identifier, PCI::RegisterOffset::BAR0);
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}
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u32 get_BAR1(Address address)
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u32 get_BAR1(DeviceIdentifier const& identifier)
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{
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return read32(address, PCI::RegisterOffset::BAR1);
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SpinlockLocker locker(identifier.operation_lock());
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return read32_locked(identifier, PCI::RegisterOffset::BAR1);
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}
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u32 get_BAR2(Address address)
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u32 get_BAR2(DeviceIdentifier const& identifier)
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{
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return read32(address, PCI::RegisterOffset::BAR2);
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SpinlockLocker locker(identifier.operation_lock());
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return read32_locked(identifier, PCI::RegisterOffset::BAR2);
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}
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u32 get_BAR3(Address address)
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u32 get_BAR3(DeviceIdentifier const& identifier)
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{
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return read16(address, PCI::RegisterOffset::BAR3);
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SpinlockLocker locker(identifier.operation_lock());
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return read32_locked(identifier, PCI::RegisterOffset::BAR3);
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}
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u32 get_BAR4(Address address)
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u32 get_BAR4(DeviceIdentifier const& identifier)
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{
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return read32(address, PCI::RegisterOffset::BAR4);
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SpinlockLocker locker(identifier.operation_lock());
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return read32_locked(identifier, PCI::RegisterOffset::BAR4);
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}
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u32 get_BAR5(Address address)
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u32 get_BAR5(DeviceIdentifier const& identifier)
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{
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return read32(address, PCI::RegisterOffset::BAR5);
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SpinlockLocker locker(identifier.operation_lock());
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return read32_locked(identifier, PCI::RegisterOffset::BAR5);
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}
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u32 get_BAR(Address address, HeaderType0BaseRegister pci_bar)
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u32 get_BAR(DeviceIdentifier const& identifier, HeaderType0BaseRegister pci_bar)
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{
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VERIFY(to_underlying(pci_bar) <= 5);
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switch (to_underlying(pci_bar)) {
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case 0:
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return get_BAR0(address);
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return get_BAR0(identifier);
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case 1:
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return get_BAR1(address);
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return get_BAR1(identifier);
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case 2:
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return get_BAR2(address);
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return get_BAR2(identifier);
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case 3:
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return get_BAR3(address);
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return get_BAR3(identifier);
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case 4:
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return get_BAR4(address);
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return get_BAR4(identifier);
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case 5:
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return get_BAR5(address);
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return get_BAR5(identifier);
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default:
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VERIFY_NOT_REACHED();
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}
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@ -133,89 +168,113 @@ BARSpaceType get_BAR_space_type(u32 pci_bar_value)
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}
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}
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void enable_bus_mastering(Address address)
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void enable_bus_mastering(DeviceIdentifier const& identifier)
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{
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auto value = read16(address, PCI::RegisterOffset::COMMAND);
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SpinlockLocker locker(identifier.operation_lock());
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auto value = read16_locked(identifier, PCI::RegisterOffset::COMMAND);
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value |= (1 << 2);
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value |= (1 << 0);
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write16(address, PCI::RegisterOffset::COMMAND, value);
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write16_locked(identifier, PCI::RegisterOffset::COMMAND, value);
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}
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void disable_bus_mastering(Address address)
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void disable_bus_mastering(DeviceIdentifier const& identifier)
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{
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auto value = read16(address, PCI::RegisterOffset::COMMAND);
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SpinlockLocker locker(identifier.operation_lock());
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auto value = read16_locked(identifier, PCI::RegisterOffset::COMMAND);
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value &= ~(1 << 2);
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value |= (1 << 0);
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write16(address, PCI::RegisterOffset::COMMAND, value);
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write16_locked(identifier, PCI::RegisterOffset::COMMAND, value);
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}
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static void write8_offsetted(Address address, u32 field, u8 value) { Access::the().write8_field(address, field, value); }
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static void write16_offsetted(Address address, u32 field, u16 value) { Access::the().write16_field(address, field, value); }
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static void write32_offsetted(Address address, u32 field, u32 value) { Access::the().write32_field(address, field, value); }
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static u8 read8_offsetted(Address address, u32 field) { return Access::the().read8_field(address, field); }
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static u16 read16_offsetted(Address address, u32 field) { return Access::the().read16_field(address, field); }
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static u32 read32_offsetted(Address address, u32 field) { return Access::the().read32_field(address, field); }
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size_t get_BAR_space_size(Address address, HeaderType0BaseRegister pci_bar)
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static void write8_offsetted(DeviceIdentifier const& identifier, u32 field, u8 value)
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{
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VERIFY(identifier.operation_lock().is_locked());
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Access::the().write8_field(identifier, field, value);
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}
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static void write16_offsetted(DeviceIdentifier const& identifier, u32 field, u16 value)
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{
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VERIFY(identifier.operation_lock().is_locked());
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Access::the().write16_field(identifier, field, value);
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}
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static void write32_offsetted(DeviceIdentifier const& identifier, u32 field, u32 value)
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{
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VERIFY(identifier.operation_lock().is_locked());
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Access::the().write32_field(identifier, field, value);
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}
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static u8 read8_offsetted(DeviceIdentifier const& identifier, u32 field)
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{
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VERIFY(identifier.operation_lock().is_locked());
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return Access::the().read8_field(identifier, field);
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}
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static u16 read16_offsetted(DeviceIdentifier const& identifier, u32 field)
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{
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VERIFY(identifier.operation_lock().is_locked());
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return Access::the().read16_field(identifier, field);
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}
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static u32 read32_offsetted(DeviceIdentifier const& identifier, u32 field)
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{
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VERIFY(identifier.operation_lock().is_locked());
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return Access::the().read32_field(identifier, field);
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}
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size_t get_BAR_space_size(DeviceIdentifier const& identifier, HeaderType0BaseRegister pci_bar)
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{
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SpinlockLocker locker(identifier.operation_lock());
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// See PCI Spec 2.3, Page 222
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VERIFY(to_underlying(pci_bar) < 6);
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u8 field = to_underlying(PCI::RegisterOffset::BAR0) + (to_underlying(pci_bar) << 2);
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u32 bar_reserved = read32_offsetted(address, field);
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write32_offsetted(address, field, 0xFFFFFFFF);
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u32 space_size = read32_offsetted(address, field);
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write32_offsetted(address, field, bar_reserved);
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u32 bar_reserved = read32_offsetted(identifier, field);
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write32_offsetted(identifier, field, 0xFFFFFFFF);
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u32 space_size = read32_offsetted(identifier, field);
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write32_offsetted(identifier, field, bar_reserved);
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space_size &= 0xfffffff0;
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space_size = (~space_size) + 1;
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return space_size;
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}
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void raw_access(Address address, u32 field, size_t access_size, u32 value)
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void raw_access(DeviceIdentifier const& identifier, u32 field, size_t access_size, u32 value)
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{
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SpinlockLocker locker(identifier.operation_lock());
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VERIFY(access_size != 0);
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if (access_size == 1) {
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write8_offsetted(address, field, value);
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write8_offsetted(identifier, field, value);
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return;
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}
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if (access_size == 2) {
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write16_offsetted(address, field, value);
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write16_offsetted(identifier, field, value);
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return;
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}
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if (access_size == 4) {
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write32_offsetted(address, field, value);
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write32_offsetted(identifier, field, value);
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return;
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}
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VERIFY_NOT_REACHED();
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}
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u8 Capability::read8(u32 field) const
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u8 Capability::read8(size_t offset) const
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{
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return read8_offsetted(m_address, m_ptr + field);
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auto& identifier = get_device_identifier(m_address);
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SpinlockLocker locker(identifier.operation_lock());
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return read8_offsetted(identifier, m_ptr + offset);
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}
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u16 Capability::read16(u32 field) const
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u16 Capability::read16(size_t offset) const
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{
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return read16_offsetted(m_address, m_ptr + field);
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auto& identifier = get_device_identifier(m_address);
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SpinlockLocker locker(identifier.operation_lock());
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return read16_offsetted(identifier, m_ptr + offset);
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}
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u32 Capability::read32(u32 field) const
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u32 Capability::read32(size_t offset) const
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{
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return read32_offsetted(m_address, m_ptr + field);
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auto& identifier = get_device_identifier(m_address);
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SpinlockLocker locker(identifier.operation_lock());
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return read32_offsetted(identifier, m_ptr + offset);
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}
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void Capability::write8(u32 field, u8 value)
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DeviceIdentifier const& get_device_identifier(Address address)
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{
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write8_offsetted(m_address, m_ptr + field, value);
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}
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void Capability::write16(u32 field, u16 value)
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{
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write16_offsetted(m_address, m_ptr + field, value);
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}
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void Capability::write32(u32 field, u32 value)
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{
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write32_offsetted(m_address, m_ptr + field, value);
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return Access::the().get_device_identifier(address);
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}
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}
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@ -12,34 +12,37 @@
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namespace Kernel::PCI {
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void write8(Address address, PCI::RegisterOffset field, u8 value);
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void write16(Address address, PCI::RegisterOffset field, u16 value);
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void write32(Address address, PCI::RegisterOffset field, u32 value);
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u8 read8(Address address, PCI::RegisterOffset field);
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u16 read16(Address address, PCI::RegisterOffset field);
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u32 read32(Address address, PCI::RegisterOffset field);
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void write8_locked(DeviceIdentifier const&, PCI::RegisterOffset field, u8 value);
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void write16_locked(DeviceIdentifier const&, PCI::RegisterOffset field, u16 value);
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void write32_locked(DeviceIdentifier const&, PCI::RegisterOffset field, u32 value);
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u8 read8_locked(DeviceIdentifier const&, PCI::RegisterOffset field);
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u16 read16_locked(DeviceIdentifier const&, PCI::RegisterOffset field);
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u32 read32_locked(DeviceIdentifier const&, PCI::RegisterOffset field);
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HardwareID get_hardware_id(PCI::Address);
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bool is_io_space_enabled(Address);
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HardwareID get_hardware_id(DeviceIdentifier const&);
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bool is_io_space_enabled(DeviceIdentifier const&);
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ErrorOr<void> enumerate(Function<void(DeviceIdentifier const&)> callback);
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void enable_interrupt_line(Address);
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void disable_interrupt_line(Address);
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void raw_access(Address, u32, size_t, u32);
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u32 get_BAR0(Address);
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u32 get_BAR1(Address);
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u32 get_BAR2(Address);
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u32 get_BAR3(Address);
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u32 get_BAR4(Address);
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u32 get_BAR5(Address);
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u32 get_BAR(Address address, HeaderType0BaseRegister);
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size_t get_BAR_space_size(Address, HeaderType0BaseRegister);
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BARSpaceType get_BAR_space_type(u32 pci_bar_value);
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void enable_bus_mastering(Address);
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void disable_bus_mastering(Address);
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void enable_io_space(Address);
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void disable_io_space(Address);
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void enable_memory_space(Address);
|
||||
void disable_memory_space(Address);
|
||||
DeviceIdentifier get_device_identifier(Address address);
|
||||
void enable_interrupt_line(DeviceIdentifier const&);
|
||||
void disable_interrupt_line(DeviceIdentifier const&);
|
||||
void raw_access(DeviceIdentifier const&, u32, size_t, u32);
|
||||
|
||||
u32 get_BAR0(DeviceIdentifier const&);
|
||||
u32 get_BAR1(DeviceIdentifier const&);
|
||||
u32 get_BAR2(DeviceIdentifier const&);
|
||||
u32 get_BAR3(DeviceIdentifier const&);
|
||||
u32 get_BAR4(DeviceIdentifier const&);
|
||||
u32 get_BAR5(DeviceIdentifier const&);
|
||||
u32 get_BAR(DeviceIdentifier const&, HeaderType0BaseRegister);
|
||||
size_t get_BAR_space_size(DeviceIdentifier const&, HeaderType0BaseRegister);
|
||||
BARSpaceType get_BAR_space_type(u32 pci_bar_value);
|
||||
void enable_bus_mastering(DeviceIdentifier const&);
|
||||
void disable_bus_mastering(DeviceIdentifier const&);
|
||||
void enable_io_space(DeviceIdentifier const&);
|
||||
void disable_io_space(DeviceIdentifier const&);
|
||||
void enable_memory_space(DeviceIdentifier const&);
|
||||
void disable_memory_space(DeviceIdentifier const&);
|
||||
|
||||
// FIXME: Remove this once we can use PCI::Capability with inline buffer
|
||||
// so we don't need this method
|
||||
DeviceIdentifier const& get_device_identifier(Address address);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -123,38 +123,26 @@ UNMAP_AFTER_INIT bool Access::initialize_for_one_pci_domain()
|
|||
}
|
||||
#endif
|
||||
|
||||
ErrorOr<void> Access::add_host_controller_and_enumerate_attached_devices(NonnullOwnPtr<HostController> controller, Function<void(DeviceIdentifier const&)> callback)
|
||||
ErrorOr<void> Access::add_host_controller_and_scan_for_devices(NonnullOwnPtr<HostController> controller)
|
||||
{
|
||||
// Note: We hold the spinlocks for a moment just to ensure we append the
|
||||
// device identifiers safely. Afterwards, enumeration goes lockless to allow
|
||||
// IRQs to be fired if necessary.
|
||||
Vector<DeviceIdentifier> device_identifiers_behind_host_controller;
|
||||
{
|
||||
SpinlockLocker locker(m_access_lock);
|
||||
SpinlockLocker scan_locker(m_scan_lock);
|
||||
auto domain_number = controller->domain_number();
|
||||
SpinlockLocker locker(m_access_lock);
|
||||
SpinlockLocker scan_locker(m_scan_lock);
|
||||
auto domain_number = controller->domain_number();
|
||||
|
||||
VERIFY(!m_host_controllers.contains(domain_number));
|
||||
// Note: We need to register the new controller as soon as possible, and
|
||||
// definitely before enumerating devices behind that.
|
||||
m_host_controllers.set(domain_number, move(controller));
|
||||
ErrorOr<void> expansion_result;
|
||||
m_host_controllers.get(domain_number).value()->enumerate_attached_devices([&](DeviceIdentifier const& device_identifier) -> IterationDecision {
|
||||
m_device_identifiers.append(device_identifier);
|
||||
auto result = device_identifiers_behind_host_controller.try_append(device_identifier);
|
||||
if (result.is_error()) {
|
||||
expansion_result = result;
|
||||
return IterationDecision::Break;
|
||||
}
|
||||
return IterationDecision::Continue;
|
||||
});
|
||||
if (expansion_result.is_error())
|
||||
return expansion_result;
|
||||
}
|
||||
|
||||
for (auto const& device_identifier : device_identifiers_behind_host_controller) {
|
||||
callback(device_identifier);
|
||||
}
|
||||
VERIFY(!m_host_controllers.contains(domain_number));
|
||||
// Note: We need to register the new controller as soon as possible, and
|
||||
// definitely before enumerating devices behind that.
|
||||
m_host_controllers.set(domain_number, move(controller));
|
||||
ErrorOr<void> error_or_void {};
|
||||
m_host_controllers.get(domain_number).value()->enumerate_attached_devices([&](EnumerableDeviceIdentifier const& device_identifier) -> IterationDecision {
|
||||
auto device_identifier_or_error = DeviceIdentifier::from_enumerable_identifier(device_identifier);
|
||||
if (device_identifier_or_error.is_error()) {
|
||||
error_or_void = device_identifier_or_error.error();
|
||||
return IterationDecision::Break;
|
||||
}
|
||||
m_device_identifiers.append(device_identifier_or_error.release_value());
|
||||
return IterationDecision::Continue;
|
||||
});
|
||||
return {};
|
||||
}
|
||||
|
||||
|
|
@ -174,19 +162,29 @@ UNMAP_AFTER_INIT void Access::rescan_hardware()
|
|||
SpinlockLocker locker(m_access_lock);
|
||||
SpinlockLocker scan_locker(m_scan_lock);
|
||||
VERIFY(m_device_identifiers.is_empty());
|
||||
ErrorOr<void> error_or_void {};
|
||||
for (auto it = m_host_controllers.begin(); it != m_host_controllers.end(); ++it) {
|
||||
(*it).value->enumerate_attached_devices([this](DeviceIdentifier device_identifier) -> IterationDecision {
|
||||
m_device_identifiers.append(device_identifier);
|
||||
(*it).value->enumerate_attached_devices([this, &error_or_void](EnumerableDeviceIdentifier device_identifier) -> IterationDecision {
|
||||
auto device_identifier_or_error = DeviceIdentifier::from_enumerable_identifier(device_identifier);
|
||||
if (device_identifier_or_error.is_error()) {
|
||||
error_or_void = device_identifier_or_error.error();
|
||||
return IterationDecision::Break;
|
||||
}
|
||||
m_device_identifiers.append(device_identifier_or_error.release_value());
|
||||
return IterationDecision::Continue;
|
||||
});
|
||||
}
|
||||
if (error_or_void.is_error()) {
|
||||
dmesgln("Failed during PCI Access::rescan_hardware due to {}", error_or_void.error());
|
||||
VERIFY_NOT_REACHED();
|
||||
}
|
||||
}
|
||||
|
||||
ErrorOr<void> Access::fast_enumerate(Function<void(DeviceIdentifier const&)>& callback) const
|
||||
{
|
||||
// Note: We hold the m_access_lock for a brief moment just to ensure we get
|
||||
// a complete Vector in case someone wants to mutate it.
|
||||
Vector<DeviceIdentifier> device_identifiers;
|
||||
NonnullRefPtrVector<DeviceIdentifier> device_identifiers;
|
||||
{
|
||||
SpinlockLocker locker(m_access_lock);
|
||||
VERIFY(!m_device_identifiers.is_empty());
|
||||
|
|
@ -198,9 +196,9 @@ ErrorOr<void> Access::fast_enumerate(Function<void(DeviceIdentifier const&)>& ca
|
|||
return {};
|
||||
}
|
||||
|
||||
DeviceIdentifier Access::get_device_identifier(Address address) const
|
||||
DeviceIdentifier const& Access::get_device_identifier(Address address) const
|
||||
{
|
||||
for (auto device_identifier : m_device_identifiers) {
|
||||
for (auto& device_identifier : m_device_identifiers) {
|
||||
if (device_identifier.address().domain() == address.domain()
|
||||
&& device_identifier.address().bus() == address.bus()
|
||||
&& device_identifier.address().device() == address.device()
|
||||
|
|
@ -211,57 +209,65 @@ DeviceIdentifier Access::get_device_identifier(Address address) const
|
|||
VERIFY_NOT_REACHED();
|
||||
}
|
||||
|
||||
void Access::write8_field(Address address, u32 field, u8 value)
|
||||
void Access::write8_field(DeviceIdentifier const& identifier, u32 field, u8 value)
|
||||
{
|
||||
VERIFY(identifier.operation_lock().is_locked());
|
||||
SpinlockLocker locker(m_access_lock);
|
||||
VERIFY(m_host_controllers.contains(address.domain()));
|
||||
auto& controller = *m_host_controllers.get(address.domain()).value();
|
||||
controller.write8_field(address.bus(), address.device(), address.function(), field, value);
|
||||
VERIFY(m_host_controllers.contains(identifier.address().domain()));
|
||||
auto& controller = *m_host_controllers.get(identifier.address().domain()).value();
|
||||
controller.write8_field(identifier.address().bus(), identifier.address().device(), identifier.address().function(), field, value);
|
||||
}
|
||||
void Access::write16_field(Address address, u32 field, u16 value)
|
||||
void Access::write16_field(DeviceIdentifier const& identifier, u32 field, u16 value)
|
||||
{
|
||||
VERIFY(identifier.operation_lock().is_locked());
|
||||
SpinlockLocker locker(m_access_lock);
|
||||
VERIFY(m_host_controllers.contains(address.domain()));
|
||||
auto& controller = *m_host_controllers.get(address.domain()).value();
|
||||
controller.write16_field(address.bus(), address.device(), address.function(), field, value);
|
||||
VERIFY(m_host_controllers.contains(identifier.address().domain()));
|
||||
auto& controller = *m_host_controllers.get(identifier.address().domain()).value();
|
||||
controller.write16_field(identifier.address().bus(), identifier.address().device(), identifier.address().function(), field, value);
|
||||
}
|
||||
void Access::write32_field(Address address, u32 field, u32 value)
|
||||
void Access::write32_field(DeviceIdentifier const& identifier, u32 field, u32 value)
|
||||
{
|
||||
VERIFY(identifier.operation_lock().is_locked());
|
||||
SpinlockLocker locker(m_access_lock);
|
||||
VERIFY(m_host_controllers.contains(address.domain()));
|
||||
auto& controller = *m_host_controllers.get(address.domain()).value();
|
||||
controller.write32_field(address.bus(), address.device(), address.function(), field, value);
|
||||
VERIFY(m_host_controllers.contains(identifier.address().domain()));
|
||||
auto& controller = *m_host_controllers.get(identifier.address().domain()).value();
|
||||
controller.write32_field(identifier.address().bus(), identifier.address().device(), identifier.address().function(), field, value);
|
||||
}
|
||||
|
||||
u8 Access::read8_field(Address address, RegisterOffset field)
|
||||
u8 Access::read8_field(DeviceIdentifier const& identifier, RegisterOffset field)
|
||||
{
|
||||
return read8_field(address, to_underlying(field));
|
||||
VERIFY(identifier.operation_lock().is_locked());
|
||||
return read8_field(identifier, to_underlying(field));
|
||||
}
|
||||
u16 Access::read16_field(Address address, RegisterOffset field)
|
||||
u16 Access::read16_field(DeviceIdentifier const& identifier, RegisterOffset field)
|
||||
{
|
||||
return read16_field(address, to_underlying(field));
|
||||
VERIFY(identifier.operation_lock().is_locked());
|
||||
return read16_field(identifier, to_underlying(field));
|
||||
}
|
||||
|
||||
u8 Access::read8_field(Address address, u32 field)
|
||||
u8 Access::read8_field(DeviceIdentifier const& identifier, u32 field)
|
||||
{
|
||||
VERIFY(identifier.operation_lock().is_locked());
|
||||
SpinlockLocker locker(m_access_lock);
|
||||
VERIFY(m_host_controllers.contains(address.domain()));
|
||||
auto& controller = *m_host_controllers.get(address.domain()).value();
|
||||
return controller.read8_field(address.bus(), address.device(), address.function(), field);
|
||||
VERIFY(m_host_controllers.contains(identifier.address().domain()));
|
||||
auto& controller = *m_host_controllers.get(identifier.address().domain()).value();
|
||||
return controller.read8_field(identifier.address().bus(), identifier.address().device(), identifier.address().function(), field);
|
||||
}
|
||||
u16 Access::read16_field(Address address, u32 field)
|
||||
u16 Access::read16_field(DeviceIdentifier const& identifier, u32 field)
|
||||
{
|
||||
VERIFY(identifier.operation_lock().is_locked());
|
||||
SpinlockLocker locker(m_access_lock);
|
||||
VERIFY(m_host_controllers.contains(address.domain()));
|
||||
auto& controller = *m_host_controllers.get(address.domain()).value();
|
||||
return controller.read16_field(address.bus(), address.device(), address.function(), field);
|
||||
VERIFY(m_host_controllers.contains(identifier.address().domain()));
|
||||
auto& controller = *m_host_controllers.get(identifier.address().domain()).value();
|
||||
return controller.read16_field(identifier.address().bus(), identifier.address().device(), identifier.address().function(), field);
|
||||
}
|
||||
u32 Access::read32_field(Address address, u32 field)
|
||||
u32 Access::read32_field(DeviceIdentifier const& identifier, u32 field)
|
||||
{
|
||||
VERIFY(identifier.operation_lock().is_locked());
|
||||
SpinlockLocker locker(m_access_lock);
|
||||
VERIFY(m_host_controllers.contains(address.domain()));
|
||||
auto& controller = *m_host_controllers.get(address.domain()).value();
|
||||
return controller.read32_field(address.bus(), address.device(), address.function(), field);
|
||||
VERIFY(m_host_controllers.contains(identifier.address().domain()));
|
||||
auto& controller = *m_host_controllers.get(identifier.address().domain()).value();
|
||||
return controller.read32_field(identifier.address().bus(), identifier.address().device(), identifier.address().function(), field);
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
#include <AK/Bitmap.h>
|
||||
#include <AK/HashMap.h>
|
||||
#include <AK/NonnullOwnPtr.h>
|
||||
#include <AK/NonnullRefPtrVector.h>
|
||||
#include <AK/Try.h>
|
||||
#include <AK/Vector.h>
|
||||
#include <Kernel/Bus/PCI/Controller/HostController.h>
|
||||
|
|
@ -33,22 +34,25 @@ public:
|
|||
static bool is_disabled();
|
||||
static bool is_hardware_disabled();
|
||||
|
||||
void write8_field(Address address, u32 field, u8 value);
|
||||
void write16_field(Address address, u32 field, u16 value);
|
||||
void write32_field(Address address, u32 field, u32 value);
|
||||
u8 read8_field(Address address, u32 field);
|
||||
u16 read16_field(Address address, u32 field);
|
||||
u32 read32_field(Address address, u32 field);
|
||||
DeviceIdentifier get_device_identifier(Address address) const;
|
||||
void write8_field(DeviceIdentifier const&, u32 field, u8 value);
|
||||
void write16_field(DeviceIdentifier const&, u32 field, u16 value);
|
||||
void write32_field(DeviceIdentifier const&, u32 field, u32 value);
|
||||
u8 read8_field(DeviceIdentifier const&, u32 field);
|
||||
u16 read16_field(DeviceIdentifier const&, u32 field);
|
||||
u32 read32_field(DeviceIdentifier const&, u32 field);
|
||||
|
||||
// FIXME: Remove this once we can use PCI::Capability with inline buffer
|
||||
// so we don't need this method
|
||||
DeviceIdentifier const& get_device_identifier(Address address) const;
|
||||
|
||||
Spinlock<LockRank::None> const& scan_lock() const { return m_scan_lock; }
|
||||
RecursiveSpinlock<LockRank::None> const& access_lock() const { return m_access_lock; }
|
||||
|
||||
ErrorOr<void> add_host_controller_and_enumerate_attached_devices(NonnullOwnPtr<HostController>, Function<void(DeviceIdentifier const&)> callback);
|
||||
ErrorOr<void> add_host_controller_and_scan_for_devices(NonnullOwnPtr<HostController>);
|
||||
|
||||
private:
|
||||
u8 read8_field(Address address, RegisterOffset field);
|
||||
u16 read16_field(Address address, RegisterOffset field);
|
||||
u8 read8_field(DeviceIdentifier const&, RegisterOffset field);
|
||||
u16 read16_field(DeviceIdentifier const&, RegisterOffset field);
|
||||
|
||||
void add_host_controller(NonnullOwnPtr<HostController>);
|
||||
bool find_and_register_pci_host_bridges_from_acpi_mcfg_table(PhysicalAddress mcfg);
|
||||
|
|
@ -61,6 +65,6 @@ private:
|
|||
mutable Spinlock<LockRank::None> m_scan_lock {};
|
||||
|
||||
HashMap<u32, NonnullOwnPtr<PCI::HostController>> m_host_controllers;
|
||||
Vector<DeviceIdentifier> m_device_identifiers;
|
||||
NonnullRefPtrVector<DeviceIdentifier> m_device_identifiers;
|
||||
};
|
||||
}
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ u16 HostController::read16_field(BusNumber bus, DeviceNumber device, FunctionNum
|
|||
return read16_field(bus, device, function, to_underlying(field));
|
||||
}
|
||||
|
||||
UNMAP_AFTER_INIT void HostController::enumerate_functions(Function<IterationDecision(DeviceIdentifier)> const& callback, BusNumber bus, DeviceNumber device, FunctionNumber function, bool recursive_search_into_bridges)
|
||||
UNMAP_AFTER_INIT void HostController::enumerate_functions(Function<IterationDecision(EnumerableDeviceIdentifier)> const& callback, BusNumber bus, DeviceNumber device, FunctionNumber function, bool recursive_search_into_bridges)
|
||||
{
|
||||
dbgln_if(PCI_DEBUG, "PCI: Enumerating function, bus={}, device={}, function={}", bus, device, function);
|
||||
Address address(domain_number(), bus.value(), device.value(), function.value());
|
||||
|
|
@ -70,7 +70,7 @@ UNMAP_AFTER_INIT void HostController::enumerate_functions(Function<IterationDeci
|
|||
InterruptLine interrupt_line = read8_field(bus, device, function, PCI::RegisterOffset::INTERRUPT_LINE);
|
||||
InterruptPin interrupt_pin = read8_field(bus, device, function, PCI::RegisterOffset::INTERRUPT_PIN);
|
||||
auto capabilities = get_capabilities_for_function(bus, device, function);
|
||||
callback(DeviceIdentifier { address, id, revision_id, class_code, subclass_code, prog_if, subsystem_id, subsystem_vendor_id, interrupt_line, interrupt_pin, capabilities });
|
||||
callback(EnumerableDeviceIdentifier { address, id, revision_id, class_code, subclass_code, prog_if, subsystem_id, subsystem_vendor_id, interrupt_line, interrupt_pin, capabilities });
|
||||
|
||||
if (pci_class == (to_underlying(PCI::ClassID::Bridge) << 8 | to_underlying(PCI::Bridge::SubclassID::PCI_TO_PCI))
|
||||
&& recursive_search_into_bridges
|
||||
|
|
@ -83,7 +83,7 @@ UNMAP_AFTER_INIT void HostController::enumerate_functions(Function<IterationDeci
|
|||
}
|
||||
}
|
||||
|
||||
UNMAP_AFTER_INIT void HostController::enumerate_device(Function<IterationDecision(DeviceIdentifier)> const& callback, BusNumber bus, DeviceNumber device, bool recursive_search_into_bridges)
|
||||
UNMAP_AFTER_INIT void HostController::enumerate_device(Function<IterationDecision(EnumerableDeviceIdentifier)> const& callback, BusNumber bus, DeviceNumber device, bool recursive_search_into_bridges)
|
||||
{
|
||||
dbgln_if(PCI_DEBUG, "PCI: Enumerating device in bus={}, device={}", bus, device);
|
||||
if (read16_field(bus, device, 0, PCI::RegisterOffset::VENDOR_ID) == PCI::none_value)
|
||||
|
|
@ -97,14 +97,14 @@ UNMAP_AFTER_INIT void HostController::enumerate_device(Function<IterationDecisio
|
|||
}
|
||||
}
|
||||
|
||||
UNMAP_AFTER_INIT void HostController::enumerate_bus(Function<IterationDecision(DeviceIdentifier)> const& callback, BusNumber bus, bool recursive_search_into_bridges)
|
||||
UNMAP_AFTER_INIT void HostController::enumerate_bus(Function<IterationDecision(EnumerableDeviceIdentifier)> const& callback, BusNumber bus, bool recursive_search_into_bridges)
|
||||
{
|
||||
dbgln_if(PCI_DEBUG, "PCI: Enumerating bus {}", bus);
|
||||
for (u8 device = 0; device < 32; ++device)
|
||||
enumerate_device(callback, bus, device, recursive_search_into_bridges);
|
||||
}
|
||||
|
||||
UNMAP_AFTER_INIT void HostController::enumerate_attached_devices(Function<IterationDecision(DeviceIdentifier)> callback)
|
||||
UNMAP_AFTER_INIT void HostController::enumerate_attached_devices(Function<IterationDecision(EnumerableDeviceIdentifier)> callback)
|
||||
{
|
||||
VERIFY(Access::the().access_lock().is_locked());
|
||||
VERIFY(Access::the().scan_lock().is_locked());
|
||||
|
|
|
|||
|
|
@ -31,12 +31,12 @@ public:
|
|||
|
||||
u32 domain_number() const { return m_domain.domain_number(); }
|
||||
|
||||
void enumerate_attached_devices(Function<IterationDecision(DeviceIdentifier)> callback);
|
||||
void enumerate_attached_devices(Function<IterationDecision(EnumerableDeviceIdentifier)> callback);
|
||||
|
||||
private:
|
||||
void enumerate_bus(Function<IterationDecision(DeviceIdentifier)> const& callback, BusNumber, bool recursive);
|
||||
void enumerate_functions(Function<IterationDecision(DeviceIdentifier)> const& callback, BusNumber, DeviceNumber, FunctionNumber, bool recursive);
|
||||
void enumerate_device(Function<IterationDecision(DeviceIdentifier)> const& callback, BusNumber bus, DeviceNumber device, bool recursive);
|
||||
void enumerate_bus(Function<IterationDecision(EnumerableDeviceIdentifier)> const& callback, BusNumber, bool recursive);
|
||||
void enumerate_functions(Function<IterationDecision(EnumerableDeviceIdentifier)> const& callback, BusNumber, DeviceNumber, FunctionNumber, bool recursive);
|
||||
void enumerate_device(Function<IterationDecision(EnumerableDeviceIdentifier)> const& callback, BusNumber bus, DeviceNumber device, bool recursive);
|
||||
|
||||
u8 read8_field(BusNumber, DeviceNumber, FunctionNumber, RegisterOffset field);
|
||||
u16 read16_field(BusNumber, DeviceNumber, FunctionNumber, RegisterOffset field);
|
||||
|
|
|
|||
|
|
@ -15,8 +15,9 @@ static Atomic<u32> s_vmd_pci_domain_number = 0x10000;
|
|||
|
||||
NonnullOwnPtr<VolumeManagementDevice> VolumeManagementDevice::must_create(PCI::DeviceIdentifier const& device_identifier)
|
||||
{
|
||||
SpinlockLocker locker(device_identifier.operation_lock());
|
||||
u8 start_bus = 0;
|
||||
switch ((PCI::read16(device_identifier.address(), static_cast<PCI::RegisterOffset>(0x44)) >> 8) & 0x3) {
|
||||
switch ((PCI::read16_locked(device_identifier, static_cast<PCI::RegisterOffset>(0x44)) >> 8) & 0x3) {
|
||||
case 0:
|
||||
break;
|
||||
case 1:
|
||||
|
|
@ -27,7 +28,7 @@ NonnullOwnPtr<VolumeManagementDevice> VolumeManagementDevice::must_create(PCI::D
|
|||
break;
|
||||
default:
|
||||
dbgln("VMD @ {}: Unknown bus offset option was set to {}", device_identifier.address(),
|
||||
((PCI::read16(device_identifier.address(), static_cast<PCI::RegisterOffset>(0x44)) >> 8) & 0x3));
|
||||
((PCI::read16_locked(device_identifier, static_cast<PCI::RegisterOffset>(0x44)) >> 8) & 0x3));
|
||||
VERIFY_NOT_REACHED();
|
||||
}
|
||||
|
||||
|
|
@ -35,7 +36,7 @@ NonnullOwnPtr<VolumeManagementDevice> VolumeManagementDevice::must_create(PCI::D
|
|||
// resource size of BAR0.
|
||||
dbgln("VMD Host bridge @ {}: Start bus at {}, end bus {}", device_identifier.address(), start_bus, 0xff);
|
||||
PCI::Domain domain { s_vmd_pci_domain_number++, start_bus, 0xff };
|
||||
auto start_address = PhysicalAddress(PCI::get_BAR0(device_identifier.address())).page_base();
|
||||
auto start_address = PhysicalAddress(PCI::get_BAR0(device_identifier)).page_base();
|
||||
return adopt_own_if_nonnull(new (nothrow) VolumeManagementDevice(domain, start_address)).release_nonnull();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#include <AK/Types.h>
|
||||
#include <AK/Vector.h>
|
||||
#include <Kernel/Debug.h>
|
||||
#include <Kernel/Locking/Spinlock.h>
|
||||
#include <Kernel/PhysicalAddress.h>
|
||||
|
||||
namespace Kernel::PCI {
|
||||
|
|
@ -38,30 +39,31 @@ enum class BARSpaceType {
|
|||
};
|
||||
|
||||
enum class RegisterOffset {
|
||||
VENDOR_ID = 0x00, // word
|
||||
DEVICE_ID = 0x02, // word
|
||||
COMMAND = 0x04, // word
|
||||
STATUS = 0x06, // word
|
||||
REVISION_ID = 0x08, // byte
|
||||
PROG_IF = 0x09, // byte
|
||||
SUBCLASS = 0x0a, // byte
|
||||
CLASS = 0x0b, // byte
|
||||
CACHE_LINE_SIZE = 0x0c, // byte
|
||||
LATENCY_TIMER = 0x0d, // byte
|
||||
HEADER_TYPE = 0x0e, // byte
|
||||
BIST = 0x0f, // byte
|
||||
BAR0 = 0x10, // u32
|
||||
BAR1 = 0x14, // u32
|
||||
BAR2 = 0x18, // u32
|
||||
SECONDARY_BUS = 0x19, // byte
|
||||
BAR3 = 0x1C, // u32
|
||||
BAR4 = 0x20, // u32
|
||||
BAR5 = 0x24, // u32
|
||||
SUBSYSTEM_VENDOR_ID = 0x2C, // u16
|
||||
SUBSYSTEM_ID = 0x2E, // u16
|
||||
CAPABILITIES_POINTER = 0x34, // u8
|
||||
INTERRUPT_LINE = 0x3C, // byte
|
||||
INTERRUPT_PIN = 0x3D, // byte
|
||||
VENDOR_ID = 0x00, // word
|
||||
DEVICE_ID = 0x02, // word
|
||||
COMMAND = 0x04, // word
|
||||
STATUS = 0x06, // word
|
||||
REVISION_ID = 0x08, // byte
|
||||
PROG_IF = 0x09, // byte
|
||||
SUBCLASS = 0x0a, // byte
|
||||
CLASS = 0x0b, // byte
|
||||
CACHE_LINE_SIZE = 0x0c, // byte
|
||||
LATENCY_TIMER = 0x0d, // byte
|
||||
HEADER_TYPE = 0x0e, // byte
|
||||
BIST = 0x0f, // byte
|
||||
BAR0 = 0x10, // u32
|
||||
BAR1 = 0x14, // u32
|
||||
BAR2 = 0x18, // u32
|
||||
SECONDARY_BUS = 0x19, // byte
|
||||
BAR3 = 0x1C, // u32
|
||||
BAR4 = 0x20, // u32
|
||||
BAR5 = 0x24, // u32
|
||||
SUBSYSTEM_VENDOR_ID = 0x2C, // u16
|
||||
SUBSYSTEM_ID = 0x2E, // u16
|
||||
EXPANSION_ROM_POINTER = 0x30, // u32
|
||||
CAPABILITIES_POINTER = 0x34, // u8
|
||||
INTERRUPT_LINE = 0x3C, // byte
|
||||
INTERRUPT_PIN = 0x3D, // byte
|
||||
};
|
||||
|
||||
enum class Limits {
|
||||
|
|
@ -213,7 +215,7 @@ private:
|
|||
|
||||
class Capability {
|
||||
public:
|
||||
Capability(Address const& address, u8 id, u8 ptr)
|
||||
Capability(Address address, u8 id, u8 ptr)
|
||||
: m_address(address)
|
||||
, m_id(id)
|
||||
, m_ptr(ptr)
|
||||
|
|
@ -222,15 +224,12 @@ public:
|
|||
|
||||
CapabilityID id() const { return m_id; }
|
||||
|
||||
u8 read8(u32) const;
|
||||
u16 read16(u32) const;
|
||||
u32 read32(u32) const;
|
||||
void write8(u32, u8);
|
||||
void write16(u32, u16);
|
||||
void write32(u32, u32);
|
||||
u8 read8(size_t offset) const;
|
||||
u16 read16(size_t offset) const;
|
||||
u32 read32(size_t offset) const;
|
||||
|
||||
private:
|
||||
Address m_address;
|
||||
const Address m_address;
|
||||
const CapabilityID m_id;
|
||||
const u8 m_ptr;
|
||||
};
|
||||
|
|
@ -245,9 +244,9 @@ AK_TYPEDEF_DISTINCT_ORDERED_ID(u8, InterruptLine);
|
|||
AK_TYPEDEF_DISTINCT_ORDERED_ID(u8, InterruptPin);
|
||||
|
||||
class Access;
|
||||
class DeviceIdentifier {
|
||||
class EnumerableDeviceIdentifier {
|
||||
public:
|
||||
DeviceIdentifier(Address address, HardwareID hardware_id, RevisionID revision_id, ClassCode class_code, SubclassCode subclass_code, ProgrammingInterface prog_if, SubsystemID subsystem_id, SubsystemVendorID subsystem_vendor_id, InterruptLine interrupt_line, InterruptPin interrupt_pin, Vector<Capability> const& capabilities)
|
||||
EnumerableDeviceIdentifier(Address address, HardwareID hardware_id, RevisionID revision_id, ClassCode class_code, SubclassCode subclass_code, ProgrammingInterface prog_if, SubsystemID subsystem_id, SubsystemVendorID subsystem_vendor_id, InterruptLine interrupt_line, InterruptPin interrupt_pin, Vector<Capability> const& capabilities)
|
||||
: m_address(address)
|
||||
, m_hardware_id(hardware_id)
|
||||
, m_revision_id(revision_id)
|
||||
|
|
@ -289,7 +288,7 @@ public:
|
|||
m_prog_if = new_progif;
|
||||
}
|
||||
|
||||
private:
|
||||
protected:
|
||||
Address m_address;
|
||||
HardwareID m_hardware_id;
|
||||
|
||||
|
|
@ -306,6 +305,38 @@ private:
|
|||
Vector<Capability> m_capabilities;
|
||||
};
|
||||
|
||||
class DeviceIdentifier
|
||||
: public RefCounted<DeviceIdentifier>
|
||||
, public EnumerableDeviceIdentifier {
|
||||
AK_MAKE_NONCOPYABLE(DeviceIdentifier);
|
||||
|
||||
public:
|
||||
static ErrorOr<NonnullRefPtr<DeviceIdentifier>> from_enumerable_identifier(EnumerableDeviceIdentifier const& other_identifier);
|
||||
|
||||
Spinlock<LockRank::None>& operation_lock() { return m_operation_lock; }
|
||||
Spinlock<LockRank::None>& operation_lock() const { return m_operation_lock; }
|
||||
|
||||
virtual ~DeviceIdentifier() = default;
|
||||
|
||||
private:
|
||||
DeviceIdentifier(EnumerableDeviceIdentifier const& other_identifier)
|
||||
: EnumerableDeviceIdentifier(other_identifier.address(),
|
||||
other_identifier.hardware_id(),
|
||||
other_identifier.revision_id(),
|
||||
other_identifier.class_code(),
|
||||
other_identifier.subclass_code(),
|
||||
other_identifier.prog_if(),
|
||||
other_identifier.subsystem_id(),
|
||||
other_identifier.subsystem_vendor_id(),
|
||||
other_identifier.interrupt_line(),
|
||||
other_identifier.interrupt_pin(),
|
||||
other_identifier.capabilities())
|
||||
{
|
||||
}
|
||||
|
||||
mutable Spinlock<LockRank::None> m_operation_lock;
|
||||
};
|
||||
|
||||
class Domain;
|
||||
class Device;
|
||||
|
||||
|
|
|
|||
|
|
@ -10,31 +10,31 @@
|
|||
|
||||
namespace Kernel::PCI {
|
||||
|
||||
Device::Device(Address address)
|
||||
: m_pci_address(address)
|
||||
Device::Device(DeviceIdentifier const& pci_identifier)
|
||||
: m_pci_identifier(pci_identifier)
|
||||
{
|
||||
}
|
||||
|
||||
bool Device::is_msi_capable() const
|
||||
{
|
||||
return AK::any_of(
|
||||
PCI::get_device_identifier(pci_address()).capabilities(),
|
||||
m_pci_identifier->capabilities(),
|
||||
[](auto const& capability) { return capability.id().value() == PCI::Capabilities::ID::MSI; });
|
||||
}
|
||||
bool Device::is_msix_capable() const
|
||||
{
|
||||
return AK::any_of(
|
||||
PCI::get_device_identifier(pci_address()).capabilities(),
|
||||
m_pci_identifier->capabilities(),
|
||||
[](auto const& capability) { return capability.id().value() == PCI::Capabilities::ID::MSIX; });
|
||||
}
|
||||
|
||||
void Device::enable_pin_based_interrupts() const
|
||||
{
|
||||
PCI::enable_interrupt_line(pci_address());
|
||||
PCI::enable_interrupt_line(m_pci_identifier);
|
||||
}
|
||||
void Device::disable_pin_based_interrupts() const
|
||||
{
|
||||
PCI::disable_interrupt_line(pci_address());
|
||||
PCI::disable_interrupt_line(m_pci_identifier);
|
||||
}
|
||||
|
||||
void Device::enable_message_signalled_interrupts()
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
#pragma once
|
||||
|
||||
#include <AK/Format.h>
|
||||
#include <AK/NonnullRefPtr.h>
|
||||
#include <AK/StringBuilder.h>
|
||||
#include <AK/Types.h>
|
||||
#include <Kernel/Bus/PCI/Definitions.h>
|
||||
|
|
@ -15,7 +16,7 @@ namespace Kernel::PCI {
|
|||
|
||||
class Device {
|
||||
public:
|
||||
Address pci_address() const { return m_pci_address; };
|
||||
DeviceIdentifier& device_identifier() const { return *m_pci_identifier; };
|
||||
|
||||
virtual ~Device() = default;
|
||||
|
||||
|
|
@ -34,10 +35,10 @@ public:
|
|||
void disable_extended_message_signalled_interrupts();
|
||||
|
||||
protected:
|
||||
explicit Device(Address pci_address);
|
||||
explicit Device(DeviceIdentifier const& pci_identifier);
|
||||
|
||||
private:
|
||||
Address m_pci_address;
|
||||
NonnullRefPtr<DeviceIdentifier> m_pci_identifier;
|
||||
};
|
||||
|
||||
template<typename... Parameters>
|
||||
|
|
@ -48,7 +49,7 @@ void dmesgln_pci(Device const& device, AK::CheckedFormatString<Parameters...>&&
|
|||
return;
|
||||
if (builder.try_append(fmt.view()).is_error())
|
||||
return;
|
||||
AK::VariadicFormatParams<AK::AllowDebugOnlyFormatters::Yes, StringView, Address, Parameters...> variadic_format_params { device.device_name(), device.pci_address(), parameters... };
|
||||
AK::VariadicFormatParams<AK::AllowDebugOnlyFormatters::Yes, StringView, Address, Parameters...> variadic_format_params { device.device_name(), device.device_identifier().address(), parameters... };
|
||||
vdmesgln(builder.string_view(), variadic_format_params);
|
||||
}
|
||||
|
||||
|
|
|
|||
20
Kernel/Bus/PCI/DeviceIdentifier.cpp
Normal file
20
Kernel/Bus/PCI/DeviceIdentifier.cpp
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*/
|
||||
|
||||
#include <AK/AnyOf.h>
|
||||
#include <AK/Error.h>
|
||||
#include <AK/NonnullRefPtr.h>
|
||||
#include <AK/RefPtr.h>
|
||||
#include <Kernel/Bus/PCI/Definitions.h>
|
||||
|
||||
namespace Kernel::PCI {
|
||||
|
||||
ErrorOr<NonnullRefPtr<DeviceIdentifier>> DeviceIdentifier::from_enumerable_identifier(EnumerableDeviceIdentifier const& other_identifier)
|
||||
{
|
||||
return adopt_nonnull_ref_or_enomem(new (nothrow) DeviceIdentifier(other_identifier));
|
||||
}
|
||||
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue